Abstract: A semiconductor device includes a regulator circuit, a wire, n load circuits, and an analog circuit. The wire is connected to the regulator circuit and including n connection nodes (n is an integer of 2 or more). The n load circuits are connected to the n connection nodes, respectively. The analog circuit is connected between the n connection nodes and the regulator circuit. The analog circuit is configured to generate an average voltage of n voltages at the n connection nodes. The regulator circuit is configured to generate an output voltage supplied to the wire based on the average voltage generated by the analog circuit.

Abstract: A semiconductor device includes a regulator circuit, a wire, n load circuits, and an analog circuit. The wire is connected to the regulator circuit and including n connection nodes (n is an integer of 2 or more). The n load circuits are connected to the n connection nodes, respectively. The analog circuit is connected between the n connection nodes and the regulator circuit. The analog circuit is configured to generate an average voltage of n voltages at the n connection nodes. The regulator circuit is configured to generate an output voltage supplied to the wire based on the average voltage generated by the analog circuit.

Abstract: According to one embodiment, a memory system includes a memory interface circuit. The memory interface circuit has delay circuits, a detection circuit, and a control circuit. One of the delay circuits applies a delay to a data signal. Another delay circuit generates, fora strobe signal, a first delay strobe signal, a second delay strobe signal, and a third delay strobe signal, each with different delay amounts. The detection circuit detects a drift in the timing of the first delay strobe signal with respect to the delayed data signal by using the delay data signal, the first delay strobe signal, the second delay strobe signal, and the third delay strobe signal. The control circuit adjusts the first delay amount, the second delay amount, and the third delay amount in a direction to compensate the drift.

Abstract: In a processor device according to the present invention, a memory access unit reads data to be processed from an external memory and writes the data to a first register group that a plurality of processors does not access among a plurality of register groups. A control unit sequentially makes each of the plurality of processors implement a same instruction, in parallel with changing an address of a register group that stores the data to be processed. A scheduler, based on specified scenario information, specifies an instruction to be implemented and a register group to be accessed for the plurality of processors, and specifies a register group to be written to among the plurality of register groups and data to be processed that is to be written for the memory access unit.

Abstract: According to one embodiment, a memory system includes a memory interface circuit. The memory interface circuit has delay circuits, a detection circuit, and a control circuit. One of the delay circuits applies a delay to a data signal. Another delay circuit generates, fora strobe signal, a first delay strobe signal, a second delay strobe signal, and a third delay strobe signal, each with different delay amounts. The detection circuit detects a drift in the timing of the first delay strobe signal with respect to the delayed data signal by using the delay data signal, the first delay strobe signal, the second delay strobe signal, and the third delay strobe signal. The control circuit adjusts the first delay amount, the second delay amount, and the third delay amount in a direction to compensate the drift.

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including a first equalizer and a clock reproduction circuit. The first equalizer boosts a data signal. The clock reproduction circuit extracts from the boosted data signal information of a pair consisting of a rise edge and a fall edge which are temporarily separated from each other by N or more times (N is an integer of two or higher) as much as a clock cycle, performs a phase adjustment based on the information about the pair of the rise edge and the fall edge, and reproduces a clock.

Abstract: In a processor device according to the present invention, a memory access unit reads data to be processed from an external memory and writes the data to a first register group that a plurality of processors does not access among a plurality of register groups. A control unit sequentially makes each of the plurality of processors implement a same instruction, in parallel with changing an address of a register group that stores the data to be processed. A scheduler, based on specified scenario information, specifies an instruction to be implemented and a register group to be accessed for the plurality of processors, and specifies a register group to be written to among the plurality of register groups and data to be processed that is to be written for the memory access unit.

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including a first equalizer and a clock reproduction circuit. The first equalizer boosts a data signal. The clock reproduction circuit extracts from the boosted data signal information of a pair consisting of a rise edge and a fall edge which are temporarily separated from each other by N or more times (N is an integer of two or higher) as much as a clock cycle, performs a phase adjustment based on the information about the pair of the rise edge and the fall edge, and reproduces a clock.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: an equalizer circuit; a decision circuit that decides a bit value of a data signal; a sampler unit including sampler circuits, the sampler circuits having different thresholds and electrically connected in parallel between the equalizer circuit and the decision circuit; a determination circuit that determines indexes indicating a degree of confidence of current output values from the sampler circuits based on the bit values of the data signals at different past timings; and an arithmetic circuit that computes scores for bit values that are candidates for a current data signal based on the determined indexes and current output values from the sampler circuits. The decision circuit selects one bit value from the candidate bit values using the scores.

Abstract: A multiprocessor device includes external memory, processors, a memory aggregate unit, register memory, a multiplexer, and an overall control unit. The memory aggregate unit aggregates memory accesses of the processors. The register memory is prepared by a number equal to the product of the number of registers managed by the processors and the maximum number of processes of the processors. The multiplexer accesses the register memory according to a command given against register access of the processors. The overall control unit extracts a parameter from the command and provides the parameter to the processors and multiplexer, and controls them, as well as has a given number of processes consecutively processed using the same command while having addressing for the register memory changed by the processors, and when the given number of processes ends, has the command switched to a next command and processing repeated for a given number of processes.

Abstract: A front linkage for a construction machine which can uniquely calculate the rotation angle of the work tool relative to the arm and which can prevent the angle detection device from being damaged by contact with the soil during digging. The front linkage has an arm, a first link pivotally connected at one end to the front end side of the arm, and at the other end to one end of a second link, and a work tool which is pivotally connected to the other end of the second link and which is pivotally connected to the arm in a further front end side than the one end portion of the first link. The first link is positioned outward along the outer width of the side wall of the arm. An angle detecting device for detecting the rotation angle of the first link relative to the arm may comprise a magnet disposed on an inner surface of the first link and a magnetic detector disposed on the side wall outer surface of the arm.

Abstract: A front linkage for a construction machine which can uniquely calculate the rotation angle of the work tool relative to the arm and which can prevent the angle detection device from being damaged by contact with the soil during digging. The front linkage has an arm, a first link pivotally connected at one end to the front end side of the arm, and at the other end to one end of a second link, and a work tool which is pivotally connected to the other end of the second link and which is pivotally connected to the arm in a further front end side than the one end portion of the first link. The first link is positioned outward along the outer width of the side wall of the arm. An angle detecting device for detecting the rotation angle of the first link relative to the arm may comprise a magnet disposed on an inner surface of the first link and a magnetic detector disposed on the side wall outer surface of the arm.

Abstract: According to one embodiment, there is provided an open-drain-type output circuit which outputs a signal of an internal circuit. The output circuit includes a first signal output terminal, a first signal line, a first floating line, a first rectifier element, and a first ESD protection circuit. The first signal line connects the first signal output terminal and the internal circuit. Potential of the first floating line is not fixed. The first rectifier element is connected between the first signal output terminal and the first floating line. The first ESD protection circuit is connected between the first floating line and ground potential.

Abstract: A multiprocessor device includes external memory, processors, a memory aggregate unit, register memory, a multiplexer, and an overall control unit. The memory aggregate unit aggregates memory accesses of the processors. The register memory is prepared by a number equal to the product of the number of registers managed by the processors and the maximum number of processes of the processors. The multiplexer accesses the register memory according to a command given against register access of the processors. The overall control unit extracts a parameter from the command and provides the parameter to the processors and multiplexer, and controls them, as well as has a given number of processes consecutively processed using the same command while having addressing for the register memory changed by the processors, and when the given number of processes ends, has the command switched to a next command and processing repeated for a given number of processes.

Abstract: According to one embodiment, there is provided an open-drain-type output circuit which outputs a signal of an internal circuit. The output circuit includes a first signal output terminal, a first signal line, a first floating line, a first rectifier element, and a first ESD protection circuit. The first signal line connects the first signal output terminal and the internal circuit. Potential of the first floating line is not fixed. The first rectifier element is connected between the first signal output terminal and the first floating line. The first ESD protection circuit is connected between the first floating line and ground potential.

Abstract: An image processing apparatus includes a blending layout information generating unit that generates blending layout information indicative of overlay information in a blended image of plural source images, a source necessity information generating unit that generates source necessity information indicative of unnecessary areas on the source image overwritten by the blending process, a source necessity information storing memory, and a source read masking unit that conducts a read masking control. A process of generating the blending layout information and the source necessity information, and a process of conducting the read masking control are executed in different frame processing periods, separately, to reduce a throughput necessary for generation of the source necessity information.

Abstract: A serial input signal is sampled in synchronization with a plurality of first clock signals to obtain a plurality of sampling data pieces. A phase comparison circuit outputs a serial phase information signal based on the sampling data pieces. A serial-parallel conversion circuit performs a serial-to-parallel conversion on the serial phase information signal in synchronization with a second clock signal having a lower frequency, to output a parallel phase information signal. A digital filtering circuit calculates phase deviation and phase advance-delay signals based on the parallel phase information signal in synchronization with the second clock signal. By these signals, a phase control amount processing circuit generates a phase control signal. The phase control signal is in synchronization with third clock signals having a higher frequency. A phase interpolation circuit adjusts the phases of the third clock signals based on the phase control signal to output the first clock signals.

Abstract: An image processing apparatus includes a blending layout information generating unit that generates blending layout information indicative of overlay information in a blended image of plural source images, a source necessity information generating unit that generates source necessity information indicative of unnecessary areas on the source image overwritten by the blending process, a source necessity information storing memory, and a source read masking unit that conducts a read masking control. A process of generating the blending layout information and the source necessity information, and a process of conducting the read masking control are executed in different frame processing periods, separately, to reduce a throughput necessary for generation of the source necessity information.

Abstract: A chip is provided with a specific signal wire and two adjacent signal wires. Output signals based on a specific signal and two adjacent signals are transmitted to the specific signal wire and the two adjacent signal wires respectively. An adjustment coefficient is stored in a memory. The adjustment coefficient is used for reducing an occurrence amount of crosstalk arising between the specific signal wire and the two adjacent signal wires. An adjustment quantity calculation portion calculates an adjustment quantity representing a degree of decrease of a slew rate of the specific signal, based on the adjustment coefficient, the specific signal and the two adjacent signals. A driver adjusts the slew rate of the specific signal based on the adjustment quantity and to transmit one of the output signals corresponding to the specific signal.

Abstract: A data transfer apparatus includes a clock generation unit to generate a clock signal, a control unit to output parallel data and a reset signal, and a plurality of transmission units. Each of the plurality of transmission units uses continuous rising edges of a bit clock to sample the reset signal multiple times so that a phase shift of the reset signal between the transmission units is reduced, and the phase of the frequency dividing clock is aligned in each transmission unit.