Abstract: A differential amplifier receives a reference voltage and a divided voltage dividing an output voltage, and outputs a control voltage in accordance with the difference between the reference voltage and the divided voltage. The control voltage output from the differential amplifier is supplied to an output amplifier. The output amplifier generates a stabilized output voltage from a high-potential-side power supply voltage in accordance with the control voltage. A P-type MOS transistor is connected to a node of the output voltage, and the MOS transistor carries a current from the node of the output voltage. A current control circuit controls a gate of the P-type MOS transistor so that the current flowing through the P-type MOS transistor becomes a constant value.

Abstract: A data transfer apparatus includes a clock generation unit to generate a clock signal, a control unit to output parallel data and a reset signal, and a plurality of transmission units. Each of the plurality of transmission units uses continuous rising edges of a bit clock to sample the reset signal multiple times so that a phase shift of the reset signal between the transmission units is reduced, and the phase of the frequency dividing clock is aligned in each transmission unit.

Abstract: A chip is provided with a specific signal wire and two adjacent signal wires. Output signals based on a specific signal and two adjacent signals are transmitted to the specific signal wire and the two adjacent signal wires respectively. An adjustment coefficient is stored in a memory. The adjustment coefficient is used for reducing an occurrence amount of crosstalk arising between the specific signal wire and the two adjacent signal wires. An adjustment quantity calculation portion calculates an adjustment quantity representing a degree of decrease of a slew rate of the specific signal, based on the adjustment coefficient, the specific signal and the two adjacent signals. A driver adjusts the slew rate of the specific signal based on the adjustment quantity and to transmit one of the output signals corresponding to the specific signal.

Abstract: A serial input signal is sampled in synchronization with a plurality of first clock signals to obtain a plurality of sampling data pieces. A phase comparison circuit outputs a serial phase information signal based on the sampling data pieces. A serial-parallel conversion circuit performs a serial-to-parallel conversion on the serial phase information signal in synchronization with a second clock signal having a lower frequency, to output a parallel phase information signal. A digital filtering circuit calculates phase deviation and phase advance-delay signals based on the parallel phase information signal in synchronization with the second clock signal. By these signals, a phase control amount processing circuit generates a phase control signal. The phase control signal is in synchronization with third clock signals having a higher frequency. A phase interpolation circuit adjusts the phases of the third clock signals based on the phase control signal to output the first clock signals.

Abstract: A multilayer interconnect configuration is formed on a semiconductor substrate where a semiconductor integrated circuit is provided. Each layer of the multilayer interconnect configuration has a plurality of pads. Except for the pads of the top layer, the area of the pads is reduced relative to the pads of the top layer. The pad area is reduced by forming a plurality of openings in the pads, or by forming a plurality of notches in the pads whereby the pads have a comb configuration. The capacitance can be significantly reduced by decreasing the area. The reduction of capacitance allows for significantly reducing the effect of a low-pass filter produced from the interconnect metal resistance and the pad capacitance, which slows down the circuit operation. Therefore the high-speed operation can avoid degradation.

Abstract: According to one embodiment, an amplifier circuit includes a clock generation circuit, a switching amplifier circuit, and a smoothing circuit. The clock generation circuit generates a pseudo random period pattern signal whose period varies. The switching amplifier circuit samples an input signal based on the pseudo random period pattern signal used as a sampling clock. The smoothing circuit smoothes an output signal of the switching amplifier circuit.

Abstract: A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data.

Abstract: A semiconductor integrated circuit has first and second delay circuits that have n (n is an integer equal to or larger than 2) delay elements connected in series, respectively, and in which an identical input signal is inputted to delay elements at a first stage and output signals of delay elements at a kth (k is an integer satisfying a condition 1?k?n?1) stage are inputted to delay elements at a k+1th stage and a detection circuit that has n edge detecting units and a readout unit and in which a jth (j is an integer satisfying a condition 1?j?n) edge detecting unit is inputted with an output signal of a delay element at a jth stage of the first delay circuit and an output signal of a delay element at an n?j+1th stage of the second delay circuit, detects whether periods of rising or falling changes of the two signals overlap, and counts a number of times of the detection, and the readout unit reads out the counted number of times of the detection.

Abstract: A spatial input operation display apparatus providing a user interface allowing input operations inside a space without requiring hands or fingers to be stopped in space, and not requiring a physical shape or space.

Abstract: An LSI internal signal observing circuit includes a pad; a monitor line connected to the pad and wired inside an LSI; a shield line wired adjacent to the monitor line and having a fixed potential; a buffer having an output enable terminal and connected to an internal node in the LSI; and a capacitor connected between an output of the buffer and the monitor line, wherein an output enable signal input to the enable terminal is controlled to set the buffer in an output enable state, and a change of a signal at the internal node is superposed on the monitor line through the capacitor and observed at the pad.

Abstract: A frequency characteristic measuring circuit is disclosed, which includes a first diode element having differential input nodes and differential output nodes, thermally coupled to a resistance element of a differential amplifying circuit having the resistance element connected between the differential output nodes, and driven by a first constant current source, a second diode element for reference driven by a second constant current source, and a detection circuit which detects a potential difference between forward voltages of the first and second diode elements to output a signal in accordance with the detected potential difference.

Abstract: A resistance adjusting circuit including a semiconductor integrated circuit includes a reference voltage generating circuit which generates a reference voltage corresponding to a resistance of an external resistor element connected to the semiconductor integrated circuit, a comparison voltage generating circuit which comprises a replica resistor circuit whose resistance is adjusted according to a resistance control signal and generates a comparison voltage corresponding to a resistance of the replica resistor circuit, a main body resistor circuit which has substantially the same configuration as that of the replica resistor circuit and whose resistance is adjusted according to the resistance control signal, and a control signal generating circuit which receives the reference and comparison voltages and converts the voltages to frequency signals corresponding to the voltages, integrates the frequency signals to produce integration data of the frequency signals, and generates the resistance control signal based

Abstract: A test circuit to test an equalizer is disclosed. Pseudo-random number data is generated by a pseudo-random number data generation unit. A weight coefficient is generated by a weight coefficient generation unit in order to set interference strength of intersymbol interference. In a pseudo-intersymbol interference data generation unit, pseudo-intersymbol interference is generated according to a bit sequence of the pseudo-random number data, and pseudo-intersymbol interference data is outputted. An amplitude of the pseudo-intersymbol interference data is changed according to the weight coefficient. A driver converts the pseudo-intersymbol interference data into a differential signal. A comparison unit compares the pseudo-random number data generated by the pseudo-random number data generation unit with output data obtained from the equalizer, when the differential signal outputted from the driver is inputted into the equalizer. A count unit counts the number of unmatched data detected by the comparison unit.

Abstract: According to the present invention, there is provided a semiconductor device comprising: a current driver which is connected to a power supply terminal, and supplies a predetermined current; a first wiring layer which is connected to an output terminal of said current driver; and a second wiring layer which is placed to oppose said first wiring layer via an insulating layer, and has a predetermined resistance value.

Abstract: A resistance adjusting circuit including a semiconductor integrated circuit includes a reference voltage generating circuit which generates a reference voltage corresponding to a resistance of an external resistor element connected to the semiconductor integrated circuit, a comparison voltage generating circuit which comprises a replica resistor circuit whose resistance is adjusted according to a resistance control signal and generates a comparison voltage corresponding to a resistance of the replica resistor circuit, a main body resistor circuit which has substantially the same configuration as that of the replica resistor circuit and whose resistance is adjusted according to the resistance control signal, and a control signal generating circuit which receives the reference and comparison voltages and converts the voltages to frequency signals corresponding to the voltages, integrates the frequency signals to produce integration data of the frequency signals, and generates the resistance control signal based

Abstract: A frequency characteristic measuring circuit is disclosed, which includes a first diode element having differential input nodes and differential output nodes, thermally coupled to a resistance element of a differential amplifying circuit having the resistance element connected between the differential output nodes, and driven by a first constant current source, a second diode element for reference driven by a second constant current source, and a detection circuit which detects a potential difference between forward voltages of the first and second diode elements to output a signal in accordance with the detected potential difference.

Abstract: A differential amplifier receives a reference voltage and a divided voltage dividing an output voltage, and outputs a control voltage in accordance with the difference between the reference voltage and the divided voltage. The control voltage output from the differential amplifier is supplied to an output amplifier. The output amplifier generates a stabilized output voltage from a high-potential-side power supply voltage in accordance with the control voltage. A P-type MOS transistor is connected to a node of the output voltage, and the MOS transistor carries a current from the node of the output voltage. A current control circuit controls a gate of the P-type MOS transistor so that the current flowing through the P-type MOS transistor becomes a constant value.

Abstract: A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data.

Abstract: A control unit 6 obtains position data from a sensor unit 1 to specify the position of the main body of an apparatus, and also obtains acceleration data from the sensor unit 1 to specify the azimuth along which the main body faces forward. Then, the control unit employs the azimuth data and the position data to calculate distance data and directional data relative to a predesignated or given position, and outputs these data as sound localization data. Based on the sound localization data, a processing unit 7 performs a stereophonic sound process for digital audio data, and generates digital audio data having directivity. A conversion unit 8 converts the digital audio data into analog audio data, and drives loudspeakers 9 and 10 to release stereophonic speech. As a result, using a speech form that is easily understood simply by listening, a direction instruction can be provided for a listener.

Abstract: A semiconductor integrated circuit has first and second delay circuits that have n (n is an integer equal to or larger than 2) delay elements connected in series, respectively, and in which an identical input signal is inputted to delay elements at a first stage and output signals of delay elements at a kth (k is an integer satisfying a condition 1?k?n?1) stage are inputted to delay elements at a k+1th stage and a detection circuit that has n edge detecting units and a readout unit and in which a jth (j is an integer satisfying a condition 1?j?n) edge detecting unit is inputted with an output signal of a delay element at a jth stage of the first delay circuit and an output signal of a delay element at an n?j+1th stage of the second delay circuit, detects whether periods of rising or falling changes of the two signals overlap, and counts a number of times of the detection, and the readout unit reads out the counted number of times of the detection.