Abstract: A voltage controlled delay circuit is comprised of a plurality of stages of delay cells and produces a 2N number of signals delayed behind a reference signal in units of time corresponding to 1/2N the delay time between the reference signal supplied to an input terminal of a first stage delay cell and a signal output from a final stage delay cell. A phase coincidence is achieved between the reference signal and the output signal from the final stage delay cell by a loop including a phase comparator, lowpass filter and voltage controlled delay circuit. An N multiplying logic circuit produces an N multiplied signal from the reference signal with only falls or rises of 2N delay signals.

Abstract: In an apparatus and method for generating a straight line using the Bresenham algorithm, when the XY coordinates of a start point and an end point of the line are given, the lattice point to be displayed can be freely selected when the desired straight line passes directly between two lattice points. A reference coordinate determination means determines a reference coordinate and a judge coordinate based on the differences in absolute values between the X coordinates of the start and end points, and the Y coordinates of the start and end points. The Bresenham values are calculated and a constant input means selectively inputs one of two constants, the inputted constant indicating which one of the two lattice points is to be displayed when the desired line passes at a midpoint of the two lattice points. Further, a constant registration means registers the constant according to each of eight combinations, such that 2.sup.8 (256) lines can be drawn.