Abstract: According to the present invention, there is provided a semiconductor device having: a switching element serially connected to a resistive element to be measured; a plurality of transistors respectively connected in parallel to a series circuit consisting of the resistive element to be measured and the switching element, which will respectively take desired resistance values when turned on; and a measurement section which measures a resistance value of a parasitic resistance which occurs so as to be coupled to the resistive element to be measured by turning off the switching element and then controlling switching operations of the plurality of transistors to change the resistance values of resistors formed by the plurality of transistors, and subsequently measures a resistance value of the resistive element to be measured based on a resistance value of the parasitic resistance by turning on the switching element while turning off the plurality of transistors.

Abstract: A data conversion processing apparatus provides flexible and multifunctional resampling processing using the general-purpose setting method of direct memory access (DMA) setting. In the data conversion processing apparatus, in response to a CPU setting parameters such as input channel information and output channel information including an address for identifying each channel, the transfer amount, and so forth, for a DMA unit, the DMA unit performs data transfer via an input channel and output channel in accordance with the parameters specified by a CPU. A transfer from a first input section to a resampling section via the DMA unit can be specified, including transfer contents from a memory to a first output section. A transfer from the first input section to the first output section is performed by two DMA transfers.

Abstract: According to the present invention, there is provided a semiconductor device comprising: a current driver which is connected to a power supply terminal, and supplies a predetermined current; a first wiring layer which is connected to an output terminal of said current driver; and a second wiring layer which is placed to oppose said first wiring layer via an insulating layer, and has a predetermined resistance value.

Abstract: A multilayer interconnect configuration is formed on a semiconductor substrate where a semiconductor integrated circuit is provided. Each layer of the multilayer interconnect configuration has a plurality of pads. Except for the pads of the top layer, the area of the pads is reduced relative to the pads of the top layer. The pad area is reduced by forming a plurality of openings in the pads, or by forming a plurality of notches in the pads whereby the pads have a comb configuration. The capacitance can be significantly reduced by decreasing the area. The reduction of capacitance allows for significantly reducing the effect of a low-pass filter produced from the interconnect metal resistance and the pad capacitance, which slows down the circuit operation. Therefore the high-speed operation can avoid degradation.

Abstract: An LSI internal signal observing circuit includes a pad; a monitor line connected to the pad and wired inside an LSI; a shield line wired adjacent to the monitor line and having a fixed potential; a buffer having an output enable terminal and connected to an internal node in the LSI; and a capacitor connected between an output of the buffer and the monitor line, wherein an output enable signal input to the enable terminal is controlled to set the buffer in an output enable state, and a change of a signal at the internal node is superposed on the monitor line through the capacitor and observed at the pad.

Abstract: A data conversion processing apparatus that makes possible flexible and multifunctional resampling processing using the general-purpose setting method of DMA setting. In the data conversion processing apparatus, when a CPU 10 sets parameters such as input channel information and output channel information including an address for identifying each channel, the transfer amount, and so forth, for a DMA 5, DMA 5 performs data transfer via an input channel and output channel in accordance with the parameters specified by CPU 10. For example, by means of these parameter settings, transfer from a first input section 30 to a resampling section 2 via DMA 5 can be specified, and also transfer of those transfer contents from memory 1 to a first output section 40 can be specified, and transfer from first input section 30 to first output section 40 is performed by means of these two DMA transfers.

Abstract: A dielectric layer is formed on a first metal layer, the dielectric layer is formed with many concave portions at the upper surface. A second metal layer is formed on the dielectric layer, the second metal layer is formed with a convex portion at a position corresponding to each of many concave portions. A capacitances is generated between the first and second metal layers. The capacitor element is composed of the first metal layer, the dielectric layer and the second metal layer. The first and second metal layers are used as power supply interconnection, the capacitor element is connected between a pair of power supply interconnections. Further, the first metal layer is connected to reference voltage, and the second metal layer is used as a pad electrode. By doing so, a capacitor element is connected between the pad electrode and the reference voltage.

Abstract: A dielectric layer is formed on a first metal layer, the dielectric layer is formed with many concave portions at the upper surface. A second metal layer is formed on the dielectric layer, the second metal layer is formed with a convex portion at a position corresponding to each of many concave portions. A capacitances is generated between the first and second metal layers. The capacitor element is composed of the first metal layer, the dielectric layer and the second metal layer. The first and second metal layers are used as power supply interconnection, the capacitor element is connected between a pair of power supply interconnections. Further, the first metal layer is connected to reference voltage, and the second metal layer is used as a pad electrode. By doing so, a capacitor element is connected between the pad electrode and the reference voltage.

Abstract: A common bias section is composed of a first series circuit having an internal resistor and an external resistor connected in series and an operational amplifier having a first input terminal connected to a reference voltage, a second input terminal connected to a Vr1 node, and an output terminal connected to the series circuit. An impedance trimming section is composed of a series circuit having an internal resistor and an impedance dummy resistor connected in series, a comparator CMP having a first input terminal connected to the Vr1 node and a second input terminal connected to a Vto1 node, a code control circuit which uses a clock signal to latch an output signal from the comparator to generate a plurality of switching codes, and a switching circuit which switch a resistance value of the impedance dummy resistor.

Abstract: A common bias section is composed of a first series circuit having an internal resistor and an external resistor connected in series and an operational amplifier having a first input terminal connected to a reference voltage, a second input terminal connected to a Vr1 node, and an output terminal connected to the series circuit. An impedance trimming section is composed of a series circuit having an internal resistor and an impedance dummy resistor connected in series, a comparator CMP having a first input terminal connected to the Vr1 node and a second input terminal connected to a Vto1 node, a code control circuit which uses a clock signal to latch an output signal from the comparator to generate a plurality of switching codes, and a switching circuit which switch a resistance value of the impedance dummy resistor.

Abstract: A detection unit detects input-request signals or receive signals that correspond to the input-request signals that are sent and received between a specific data-processing apparatus and another apparatus. A judgment unit then determines whether the data-processing apparatus is performing a specific process, based on the status of the data-processing apparatus and detection results from the detection unit. A supply-control unit controls whether or not to supply a synchronization clock to the data-processing means according to judgment results from the judgment unit.

Abstract: A detection unit detects input-request signals or receive signals that correspond to the input-request signals that are sent and received between a specific data-processing apparatus and another apparatus. A judgment unit then determines whether the data-processing apparatus is performing a specific process, based on the status of the data-processing apparatus and detection results from the detection unit. A supply-control unit controls whether or not to supply a synchronization clock to the data-processing means according to judgment results from the judgment unit.

Abstract: A data extraction circuit includes a determination circuit which determines a sampling clock which is optimum for reproduction of reception data supplied from the exterior based on phase information of multiphase clocks corresponding to an edge of the reception data. Further, the data extraction circuit includes a selection circuit which selects one clock which is optimum for reproduction of the reception data according to the multi-phase clocks based on the result of determination in the determination circuit. In addition, the data extraction circuit includes a reproduction circuit which reproduces the reception data according to the one optimum clock selected by the selection circuit.

Abstract: A voltage-controlled oscillator comprises a level converting circuit, an amplitude controller, a voltage-controlled oscillation section having differential delay cells connected in a ring form, and an output level converting circuit. The level converting circuit has limiters which respectively limit a maximum value and a minimum value of a control current. Those limiters permit only a region where the voltage-controlled oscillation section properly performs its oscillating operation to be used.

Abstract: A delay locked loop has a voltage-controlled delay section and a mis-lock detecting circuit. The voltage-controlled delay sections comprises a plurality of controlled delay circuits, including a specific one. In the mis-lock detecting circuit, there are generated pulse signals, each having a pulse width equivalent to the delay time between the delayed signals output from the adjacent two of the controlled delay circuits preceding the specific controlled delayed circuit. Another pulse signal is generated, which has a pulse width equivalent to the delay time between the delayed signals output from adjacent two of the specific controlled delay circuit and the other controlled delay circuits following the specific one. These pulse signals are added, generating a pulse signal. The number of pulses this pulse signal has per a unit time is compared with the number of pulses a reference signal has per the unit time, thereby detecting whether the delay locked loop is normally locked or not.

Abstract: An image data format conversion apparatus comprises: a memory storing image data; a data reading means reading image data from the memory to output it; a format converting means converting the image data output from the data reading means to a predetermined format to output it or making the image data pass through without converting it; a vertical filter vertically interpolating the image data output from the format converting means by filtering operation to output the data or making the image data pass through without interpolating it; a horizontal filter vertically interpolating the image data output from the vertical filter by filtering operation to output the data or making the image data pass through without interpolating it; an image synthesizing means performing logic operation for image data output from the filter, and synthesizing the image data to output it; and an image output means outputting the image data from the image synthesizing means to a designated display unit.

Abstract: In a frequency multiplier which generates a multiple output of a reference signal, a reference signal and its inverted signal are propagated through a pair of delay circuits each including a given number of delay cells connected in cascade. The delay cells delay a signal by time t when a control signal is at a high level and delay a signal by time 2t when a control signal is at a low level. The outputs of the delay circuits are added together by an adder circuit to generate a multiple output without using a low-pass filter but by non-feedback control.

Abstract: A voltage controlled oscillator includes plural cascade-connected unit circuits supplied with selection signals corresponding to an oscillation frequency. Each unit circuit includes a voltage controlled delay circuit, selection circuit and adder circuit. The selection circuit has a first input terminal supplied with an output signal of the voltage controlled delay circuit and a second input terminal supplied with the selection signal. The adder circuit has a first input terminal supplied with an output signal of the selection circuit, a second input terminal supplied with a feedback signal from a next-stage one of the unit circuits and a third input terminal supplied with the selection signal. The adder circuit adds signals supplied to its first and second input terminals to form a feedback signal. The output signal of the voltage controlled delay circuit in each unit circuit is supplied to the voltage controlled delay circuit in the next-stage one of the unit circuits.

Abstract: An object is to keep the oscillation gain nearly constant and attain an oscillation frequency with high stability and low jitter. A voltage controlled oscillator circuit (VCO) is constructed by a VCO control circuit and a ring oscillator. The VCO control circuit has two input terminals (n input, w input). The VC control circuit multiplies the n input by the w input, and outputs a control signal (PMOS n input, NMOS n input) obtained by adding the result of multiplication to the n input. The ring oscillator is constructed by delay circuits of an odd number of stages serially connected.

Abstract: A frequency multiplying circuit includes a plurality of frequency multipliers in a series array. The multiplying ratio of the initial stage frequency multiplier is the greatest compared with the remaining frequency multiplier or multipliers. Further, at least one of the frequency multipliers uses a voltage controlled delay circuit.