Patents by Inventor Shuichi Tsukada
Shuichi Tsukada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085834Abstract: An image forming system includes an image forming apparatus including an image forming unit and a fixing unit; a folding processing portion; a pressure-bonding portion; and an input portion capable of selecting a pressure-bonding mode in which a pressure-bonding print prepared by subjecting the recording material to pressure-bonding processing by the folding processing portion and the pressure-bonding portion and capable of selecting a layout of the toner image formed on the recording material. When the pressure-bonding mode is selected, the layout depending on the pressure-bonding mode is selected.Type: ApplicationFiled: August 31, 2023Publication date: March 14, 2024Inventors: SHUICHI TAMURA, NAOYUKI YAMAMOTO, TOHRU NAKAEGAWA, KENICHIRO KITAJIMA, KOTA MORI, YOSHIRO TSUKADA
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Publication number: 20240085843Abstract: An image forming system includes an image forming apparatus including a fixing unit, a folding processing portion, and a pressure-bonding portion. A first recording material having a first basis weight is fixed at a first temperature by the fixing unit and then is pressure-bonded by the pressure-bonding portion after a lapse of a first period. A second recording material having a second basis weight is fixed at a second temperature by the fixing unit and then is pressure-bonded by the pressure-bonding portion after a lapse of a second period. The second basis weight is larger than the first basis weight. The second temperature is higher than the first temperature. The second period is longer than the first period.Type: ApplicationFiled: August 4, 2023Publication date: March 14, 2024Inventors: NAOYUKI YAMAMOTO, KENICHIRO KITAJIMA, YOSHIRO TSUKADA, TOHRU NAKAEGAWA, KOTA MORI, SHUICHI TAMURA
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Patent number: 11709523Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.Type: GrantFiled: September 27, 2021Date of Patent: July 25, 2023Inventors: Kenji Asaki, Shuichi Tsukada
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Patent number: 11705888Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.Type: GrantFiled: November 2, 2020Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Yasuo Satoh, Hiroki Takahashi, Shuichi Tsukada, Yuan He
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Publication number: 20230170013Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.Type: ApplicationFiled: March 21, 2022Publication date: June 1, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Tetsuya Arai, Shuichi Tsukada, Shun Nishimura, Yoshinori Matsui
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Patent number: 11349479Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.Type: GrantFiled: February 12, 2019Date of Patent: May 31, 2022Assignee: Micron Technology, Inc.Inventors: Hiroyuki Matsuno, Shuichi Tsukada
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Publication number: 20220011809Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Kenji Asaki, Shuichi Tsukada
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Patent number: 11176973Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFB) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFB provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.Type: GrantFiled: December 23, 2020Date of Patent: November 16, 2021Assignee: Micron Technology, Inc.Inventors: Hiroyuki Matsuno, Shuichi Tsukada
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Patent number: 11132015Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.Type: GrantFiled: February 8, 2019Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventors: Kenji Asaki, Shuichi Tsukada
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Patent number: 11057038Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.Type: GrantFiled: October 17, 2019Date of Patent: July 6, 2021Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Shuichi Tsukada, Junki Taniguchi
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Publication number: 20210201967Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFB) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFB provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.Type: ApplicationFiled: December 23, 2020Publication date: July 1, 2021Applicant: Micron Technology, Inc.Inventors: Hiroyuki Matsuno, Shuichi Tsukada
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Patent number: 10985753Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.Type: GrantFiled: December 21, 2018Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Kenji Asaki, Shuichi Tsukada
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Publication number: 20210111706Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.Type: ApplicationFiled: November 2, 2020Publication date: April 15, 2021Inventors: Yasuo Satoh, Hiroki Takahashi, Shuichi Tsukada, Yuan He
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Patent number: 10902892Abstract: Disclosed herein is an apparatus that includes first and second signal lines; a first differential amplifier having an inverting input node receiving an input signal, a non-inverting input node receiving a reference potential, and an output node connected to the first signal line; a second differential amplifier having an inverting input node receiving the reference potential, a non-inverting input node receiving the input signal, and an output node connected to the second signal line; a level shift circuit cross-coupled to the first and second signal lines; a first replica circuit connected to the first signal line; a second replica circuit connected to the second signal line; and a first switch circuit configured to activate one of the level shift circuit, the first replica circuit, and the second replica circuit.Type: GrantFiled: March 18, 2019Date of Patent: January 26, 2021Assignee: Micron Technology, Inc.Inventor: Shuichi Tsukada
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Patent number: 10886898Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.Type: GrantFiled: October 10, 2019Date of Patent: January 5, 2021Assignee: Micron Technology, Inc.Inventors: Yasuo Satoh, Hiroki Takahashi, Shuichi Tsukada, Yuan He
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Patent number: 10878858Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFE) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFE provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.Type: GrantFiled: February 14, 2019Date of Patent: December 29, 2020Assignee: Micron Technology, Inc.Inventors: Hiroyuki Matsuno, Shuichi Tsukada
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Publication number: 20200302977Abstract: Disclosed herein is an apparatus that includes first and second signal lines; a first differential amplifier having an inverting input node receiving an input signal, a non-inverting input node receiving a reference potential, and an output node connected to the first signal line; a second differential amplifier having an inverting input node receiving the reference potential a non-inverting input node receiving the input signal, and an output node connected to the second signal line, a level shift circuit cross-coupled to the first and second signal lines; a first replica circuit connected to the first signal line; a second replica circuit connected to the second signal line; and a first switch circuit configured to activate one of the level shift circuit, the first replica circuit, and the second replica circuit.Type: ApplicationFiled: March 18, 2019Publication date: September 24, 2020Applicant: MICRON TECHNOLOGY, INC.Inventor: Shuichi Tsukada
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Publication number: 20200265879Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFE) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFE provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.Type: ApplicationFiled: February 14, 2019Publication date: August 20, 2020Applicant: Micron Technology, Inc.Inventors: Hiroyuki Matsuno, Shuichi Tsukada
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Publication number: 20200257331Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.Type: ApplicationFiled: February 8, 2019Publication date: August 13, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Kenji Asaki, Shuichi Tsukada
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Publication number: 20200052698Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.Type: ApplicationFiled: October 17, 2019Publication date: February 13, 2020Applicant: Micron Technology, Inc.Inventors: Tetsuya Arai, Shuichi Tsukada, Junki Taniguchi