Abstract: A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.

Abstract: A semiconductor device that needs a relatively long time to control a write operation and the like is reduced in size. The semiconductor device includes: first and second bit line control circuits which are arranged to correspond to first and second memory cell arrays, respectively; a control signal line that is connected to the first and second bit line control circuits in common and transmits a first control signal; and control signal lines that are connected to the first and second bit line control circuits, respectively, and transmit second and third control signals, respectively. The first bit line control circuit performs an operation control on the first memory cell array when the first and second control signals are activated. The second bit line control circuit performs an operation control on the second memory cell array when the first and third control signals are activated.

Abstract: A semiconductor device includes a plurality of drain lines each being commonly connected to first nodes of a plurality of memory cells, a plurality of bit lines respectively connected to second nodes of the memory cells, a source line, a transistor that connects the drain lines to the source line, and a transistor that connects the source line to a ground potential in response to an access to the memory cell. Under control in which the memory cells are all deactivated, the semiconductor device controls the drain line to a drain potential that is higher than the ground potential, and controls the source line to be in a floating state by deactivating the transistors.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first insulating film region that is embedded in a trench formed on the semiconductor substrate, a gate electrode that covers a lower surface of the first insulating film region, and a gate insulating film that is provided between the gate electrode and the semiconductor substrate. The semiconductor device further includes a first diffusion region that covers a first side surface of the first insulating film region, a second diffusion region that covers a second side surface of the first insulating film region, and a third diffusion region that covers an upper surface of the second diffusion region. A selective element includes a field-effect transistor that is constituted by the gate electrode, the first diffusion region, and the second diffusion region, and a bipolar transistor that is constituted by the substrate and the second and third diffusion regions.

Abstract: A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell.

Abstract: A semiconductor memory device comprises: a phase change element (RP) and a memory cell transistor (MN0) that controls writing and reading of data with respect to the phase change element (RP); the memory cell transistor (MN0) supplies a current to the phase change element (RP) based on a first potential (VPS) in a first (read) operation mode, and in a second (write) operation mode supplies a current based on the first potential (VPS), and subsequently supplies a current based on a second potential (VPP) higher than the first potential (VPS). In a write operation, consumed current is reduced.

Abstract: A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal.

Abstract: A memory cell potentially including a retention fault attributable to a random change over time of data retention capability is screened by applying a bias to a gate electrode such that holes are accumulated on an interface of a substrate that is a component of a memory cell transistor on the side of the gate electrode and, after applying the bias, performing a pause-refresh test for inspecting the data retention capability of the memory cell.

Abstract: The semiconductor memory device includes a control circuit that performs control of reading data from and writing data into each memory cell. The control circuit includes a flip-flop circuit that stores the data read from the memory cell and stores the data to be written into the memory cell and a dynamic type holding circuit connected to the flip-flop circuit through a switch. The dynamic-type holding circuit temporarily stores the data read from the memory cell. When the data read from the memory cell and then held in the holding circuit is different from the data in the flip-flop circuit to be written, supplied from an outside at a time of writing into the memory cell, control is performed so that the data in the flip-flop circuit is written into the memory cell.

Abstract: A semiconductor device includes a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction, a plurality of source lines formed along a third direction which is different from the first and the second directions, and a source line control circuit serving as a driving arrangement selectively driving the plurality of source lines.

Abstract: A semiconductor device includes: a first read/write amplifier; a second read/write amplifier; a first group of bit lines belonging to the first read/write amplifier; a second group of bit lines belonging to the second read/write amplifier and mixed with the first group of bit lines. One of the first group of bit lines and one of the second group of bit lines are selected in parallel. A reference potential is supplied to at least one of the first non-selected bit lines adjacent to the first selected bit line selected from the first group of bit lines, and to at least one of the second non-selected bit lines adjacent to the second selected bit line selected from the first group of bit lines. At least one of remaining ones of the first and second non-selected bit lines is set into a floating state.

Abstract: In the present invention, an inspection contact structure is attached to the lower surface side of a circuit board in a probe card. In the inspection contact structure, elastic sheets with protruding conductive portions are respectively attached to both surfaces of a silicone substrate. The silicone substrate is formed with current-carrying paths passing therethrough in the vertical direction, and the sheet conductive portions are in contact with the current-carrying paths from above and below. The conductive portions on the upper side are in contact with connecting terminals of the circuit board. At the time of inspection of electric properties of a wafer, electrode pads on the wafer are pressed against the conductive portions on the lower side and thereby brought into contact with them.

Abstract: In the present invention, an inspection contact structure is attached to the lower surface side of a circuit board in a probe card. In the inspection contact structure, elastic sheets with protruding conductive portions are respectively attached to both surfaces of a silicone substrate. The silicone substrate is formed with current-carrying paths passing therethrough in the vertical direction, and the sheet conductive portions are in contact with the current-carrying paths from above and below. The conductive portions on the upper side are in contact with connecting terminals of the circuit board. At the time of inspection of electric properties of a wafer, electrode pads on the wafer are pressed against the conductive portions on the lower side and thereby brought into contact with them.

Abstract: A current limit circuit comprising: a current limit element for limiting an output current level to within a predetermined range of a limiting current and including a first PMOS transistor having a source to which a predetermined voltage is applied and a drain through which the output current is supplied; and a gate voltage generating circuit for generating a gate voltage by a feedback control such that a difference between the predetermined voltage and a gate voltage of the first PMOS transistor coincides with a threshold voltage of a second PMOS transistor having approximately the same characteristic as that of the first PMOS transistor in a state in which a predetermined current is flowing through the second PMOS transistor.

Abstract: A current limit circuit comprising: a current limit element for limiting an output current level to within a predetermined range of a limiting current and including a first PMOS transistor having a source to which a predetermined voltage is applied and a drain through which the output current is supplied; and a gate voltage generating circuit for generating a gate voltage by a feedback control such that a difference between the predetermined voltage and a gate voltage of the first PMOS transistor coincides with a threshold voltage of a second PMOS transistor having approximately the same characteristic as that of the first PMOS transistor in a state in which a predetermined current is flowing through the second PMOS transistor.

Abstract: A method for manufacturing a pneumatic tire, including the steps of intermittently crimping volume adjusting members on both side sections of a sheet inner liner material in a longitudinal direction thereof beforehand, winding the inner liner material on an outer peripheral side of a forming drum, winding a sheet carcass material on an outer peripheral side of the inner liner material, forming an unvulcanized tire containing the inner liner material and the carcass material, and vulcanizing the unvulcanized tire. The volume adjusting members are intermittently arranged in a tire circumferential direction between the inner liner material and the carcass material.

Abstract: A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP1, capacitor C1, MOS transistor TP2, and control circuit. MOS transistor TP1 is turned on when overdriving begins, and is designed to supply voltage of power supply VDD1 to parallel-connected sense amplifiers. Capacitor C1 accumulates electrical charges referenced to in association with electrical charges supplied to sense the amplifiers via MOS transistor TP1. MOS transistor TP2 is turned on when overdriving begins, to supply voltage of power supply VDD1 to capacitor C1. The control circuit controls so that MOS transistors TP1, TP2 are turned off when the capacitor potential has reached voltage VREF1. There is also provided a MOS transistor turned on after the MOS transistors TP1, TP2 are turned off to supply a power supply voltage equal to the voltage VREF1 to the plural sense amplifiers.

Abstract: A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.

Abstract: The present invention enables screening of the so-called variable retention time (VRT) failure, namely a retention failure occurring in a DRAM due to fluctuation of a data retention time like a random telegraph noise. A pause/refresh test for checking a data retention function is repeated at all memory cells of a chip so that memory cells at which the retention failure due to random fluctuation of the data retention capability over time may occur is subjected to screening.

Abstract: In the present invention, an inspection contact structure is attached to the lower surface side of a circuit board in a probe card. In the inspection contact structure, elastic sheets with protruding conductive portions are respectively attached to both surfaces of a silicone substrate. The silicone substrate is formed with current-carrying paths passing therethrough in the vertical direction, and the sheet conductive portions are in contact with the current-carrying paths from above and below. The conductive portions on the upper side are in contact with connecting terminals of the circuit board. At the time of inspection of electric properties of a wafer, electrode pads on the wafer are pressed against the conductive portions on the lower side and thereby brought into contact with them.