Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

Abstract: A nonvolatile memory device having a blocking insulating layer with an excellent data retention property and a method of fabricating the same are provided. The nonvolatile memory device may include a semiconductor substrate having a channel region formed therein; and a gate stack including a tunneling insulating layer, a charge storing layer, a blocking insulating layer and a control gate electrode sequentially stacked on the channel region of the semiconductor substrate. The blocking insulating layer may comprise a lanthanum aluminum oxide having a formula of La2-xAlxOy and the composition parameter x may be 1<x<2.

Abstract: Provided are flash memory devices. Embodiments of such devices may include a tunnel insulator formed on a substrate, a charge-storage layer formed on the tunnel insulator, a lower buffer layer formed on the charge-storage layer, a blocking layer formed on the lower buffer layer, and a first gate electrode formed on the blocking layer. Such devices may include second gate electrode formed on the first gate electrode, such that the lower buffer layer includes a silicon-free insulator, the blocking layer includes oxides or ternary lanthanum compounds, and the oxides or ternary lanthanum compounds include lanthanide elements.

Abstract: In one aspect, a memory cell includes a plurality of dielectric layers located within a charge storage gate structure. At least one of the dielectric layers includes an dielectric material including oxygen, and nano regions including oxygen embedded in the dielectric material, where an oxygen concentration of the dielectric material is the greater than an oxygen concentration of the nano regions. In another aspect, at least one of the dielectric layers includes a dielectric material and nano regions embedded in the dielectric material, where an atomic composition of the dielectric material is the same as the atomic composition of the nano regions, and a density of the dielectric material is the greater than a density of the nano regions.

Abstract: A cleaning probe capable of providing uniform cleaning to an entire wafer while not damaging the edge portion of the wafer, and a megasonic cleaning apparatus having the cleaning probe are provided. The cleaning probe comprises a front portion located near the center of the wafer, a rear portion connected to a piezoelectric transducer, and a protrusion located between the rear portion and the front portion, located on an edge portion of the wafer, and having a larger cross section width than the front portion.

Abstract: A method of manufacturing a non-volatie memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density the lower dielectric layer, and forming a middle dielectric layer having an energy band gap smaller than that of the lower dielectric layer on the first heat-treated lower dielectric layer. The method further includes forming an upper dielectric layer including a material substantially identical to that of the lower dielectric layer on the middle dielectric layer, performing a second heat treatment process to densify the middle dielectric layer and the upper dielectric layer and forming a conductive layer on the second heat-treated upper dielectric layer.

Abstract: A method of manufacturing a non-volatile memory device includes forming a tunnel isolation layer forming a tunnel isolation layer on a substrate, forming a conductive pattern on the tunnel isolation layer, forming a lower silicon oxide layer on the conductive pattern, treating a surface portion of the lower silicon oxide layer with a nitridation treatment to form a first silicon oxynitride layer on the lower silicon oxide layer, forming a metal oxide layer on the first silicon oxynitride layer, forming an upper silicon oxide layer on the metal oxide layer, and forming a conductive layer on the upper silicon oxide layer.

Abstract: A method of forming a flash memory device can include forming a tunneling oxide film on a semiconductor substrate, forming a charge storing layer on the tunneling oxide film, forming a first blocking oxide film on the charge storing layer at a first temperature, forming a second blocking oxide film on the first blocking oxide film at a second temperature higher than the first temperature, and forming a gate electrode on the second blocking oxide film.

Abstract: In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

Abstract: In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

Abstract: An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting layer on the first electrode; generating an acoustic stress wave at the interface between the substrate and semiconductor layer, thereby separating the substrate from the semiconductor layer; and forming a second electrode on the semiconductor layer exposed by the separation of the substrate.

Abstract: A method of fabricating a floating trap type nonvolatile memory device is provided. The method includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequentially stacked; thermally annealing a resultant substrate including the cell gate insulating layer in a temperature range of 810-100° C.; and forming a gate electrode on the thermally annealed cell gate insulating layer.

Abstract: Provided are an electroplating apparatus and an electroplating method using the electroplating apparatus. The electroplating apparatus includes an electroplating bath, an anode, a cathode, and a conductor. An electroplating solution is supplied into the electroplating bath. An electroplating solution entrance and an electroplating solution exit are formed in the electroplating bath. The anode is installed inside the electroplating bath. The cathode is spaced a predetermined gap apart from and opposite to the anode. A layer that is to electroplated is installed on the cathode. The conductor is installed between the anode and the cathode.

Abstract: The mammary gland-specific expression systems developed by the present inventors, named pGbc, pGbc_L and pGbc_S were deposited under the Budapest Treaty on the International Recognition of the Deposit of Microorganisms for the Purpose of Patent Procedure in the Korean Collection for Type Cultures (KCTC), Korean Research Institute of Bioscience and Biotechnology at 52, Oun-dong, Yusong-Ku, Taejon 305–333, Republic of Korea, on Aug. 17, 1998, and the accession deposit Nos. KCTC 0515BP, 0514BP and 0513BP were issued, respectively. All restructions on the availability to the public of the deposited materials will be irrevocably removed upon the granting of a patent.

Abstract: A cleaning probe capable of providing uniform cleaning to an entire wafer while not damaging the edge portion of the wafer, and a megasonic cleaning apparatus having the cleaning probe are provided. The cleaning probe comprises a front portion located near the center of the wafer, a rear portion connected to a piezoelectric transducer, and a protrusion located between the rear portion and the front portion, located on an edge portion of the wafer, and having a larger cross section width than the front portion.

Abstract: A method for distributively managing the CRL in a certifying system to certify the validity of a subscriber in an open communications network such as Internet, includes the steps of registering the certificate policy statement for the CRL by determining the distribution interval of the CRL; setting the structure of the certificate of the subscriber to issue the certificate according to the registered certificate policy statement; attesting the certificate by applying the distribution point mechanism according to the distribution interval to the CRL; and revoking the certificate by using the distribution points to revise the CRL displayed.

Abstract: Briefly, a preferred embodiment of the present invention includes a metal-insulator-metal (MIM) capacitor including a bottom layer of conductive material formed by depositing this conductive material on a substrate. A dielectric material is then formed on the bottom conductive layer, wherein the dielectric material is preferably an HfO2 dielectric doped with lanthamide material, more preferably Th doped HfO2 with a Th concentration in the range of 0 to 6% and more particularly substantially 4%. A top conductive layer is formed on top of the dielectric.

Abstract: There are disclosed mammary gland tissue-specific expression systems using the promoter site for the &bgr;-casein gene of Korean native goats, by use of which physiological activating substances can be produced. In each of the expression systems, that is, novel plasmids pGbc, pGbc_L and pGbc_S (deposition Nos. KCTC 0515BP, 0514BP and 0513BP, respectively), a &bgr;-casein gene expression-regulating region, a physiological activating substance gene and a termination-regulating region are linked. Human granulocyte colony stimulating factor (hG-CSF) or human granulocyte macrophage colony stimulating factor (hGM-CSF) can be produced in HC11 cells, a mouse mammary gland tissue-derived cell line, and in the milk secreted from the transgenic mice by use of a hG-CSF or hGM-CSF gene-carrying pGbc, pGbc_L or pGbc_S in transfection into cell and microinjection to mouse. The proteins are those which experience the posttranslational modification and maintain their normal activity in the human body.

Abstract: There are disclosed mammary gland tissue-specific expression systems using the promoter site for the &bgr;-casein gene of Korean native goats, by use of which physiological activating substances can be produced. In each of the expression systems, that is, novel plasmids pGbc, pGbc_L and pGbc_S (deposition Nos. KCTC 0515BP, 0514BP and 0513BP, respectively), a &bgr;-casein gene expression-regulating region, a physiological activating substance gene and a termination-regulating region are linked. Human granulocyte colony stimulating factor (hG-CSF) or human granulocyte macrophage colony stimulating factor (hGM-CSF) can be produced in HC11 cells, a mouse mammary gland tissue-derived cell line, and in the milk secreted from the transgenic mice by use of a hG-CSF or hGM-CSF gene-carrying pGbc, pGbc_L or pGbc_S in transfection into cell and microinjection to mouse. The proteins are those which experience the posttranslational modification and maintain their normal activity in the human body.

Abstract: A transgenic goat zygote is developed from a goat zygote comprising a nucleic acid construct containing a nucleotide sequence of a goat &bgr;-casein promoter and a nucleotide sequence encoding hG-CSF, which produces milk containing a high concentration of biologically active hG-CSF.