Abstract: A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

Abstract: A semiconductor manufacturing apparatus includes a loadlock module including a loadlock chamber in which a substrate container is received, wherein the loadlock module is configured to switch an internal pressure of the loadlock chamber between atmospheric pressure and a vacuum; and a transfer module configured to transfer a substrate between the substrate container received in the loadlock chamber and a process module for performing a semiconductor manufacturing process on the substrate, wherein the loadlock module includes a purge gas supply unit configured to supply a purge gas into the substrate container through a gas supply line connected to the substrate container; and an exhaust unit configured to discharge a gas in the substrate container through an exhaust line connected to the substrate container.

Abstract: A semiconductor memory device includes an electrode structure including a plurality of gate conductive films stacked on a substrate and a channel array in which a plurality of channel columns passing through the electrode structure are arranged in a second direction. The plurality of channel columns may include a first column whose uppermost plane has a first shape and a second column whose uppermost plane has a second shape. N (N is a natural number equal to more than 1) first columns and N second columns are alternately arranged in a first direction different from the second direction.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.

Abstract: A semiconductor memory device includes a memory cell array (MCA) and a pass transistor unit (PTU). The MCA includes memory block(s) that has source selection line(s) (SSL), word lines (WLs), drain selection line(s) (DSL), and dummy WL(s) (DWL). The PTU includes source pass transistor(s) to selectively transmit a source driving signal (source DS) to the SSL, memory pass transistors (MPTs) to selectively transmit a WL DS to the WLs, respectively, drain pass transistor(s) (PT) to selectively transmit a drain DS to the DSL, and dummy PT(s) to selectively transmit a DWL DS to the DWL. The source DS, the WL DS, the drain DS, and the DWL DS may each be associated with a respective voltage range. Sizes of the source PT, the MPTs, the drain PT, and the dummy PTs are set based on the respective voltage ranges.

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

Abstract: A semiconductor memory device includes a cell string with a plurality of selection transistors, a plurality of dummy transistors and a plurality of memory cell transistors coupled in series therein and a pass transistor (TR) unit with a plurality of pass transistors that transmit a plurality of driving signals to the cell string. The pass TR unit includes a plurality of first pass transistors transmitting a first driving signal with a first level voltage, among the plurality of driving signals, to the plurality of selection transistors, respectively, and a plurality of second pass transistors transmitting a second driving signal with a second level voltage that is higher than the first level voltage, among the plurality of driving signals, to a plurality of dummy transistors, respectively. Each of the second pass transistors has a larger channel area than each of the first pass transistors.

Abstract: An apparatus for attaching a pad on or to an edge ring includes a chamber defining a space for attaching a pad on or to an edge ring, a pad support within the chamber and supporting the pad thereon, an edge ring support within the chamber and facing the pad support, the edge ring support securing the edge ring thereon, a driving system connected to at least one of the pad support and the edge ring support and configured to move the edge ring support relative to the pad support, and a vacuum exhaust system configured to create a vacuum atmosphere within the chamber.

Abstract: A semiconductor memory device includes an electrode structure including a plurality of gate conductive films stacked on a substrate and a channel array in which a plurality of channel columns passing through the electrode structure are arranged in a second direction. The plurality of channel columns each include a first column whose uppermost plane has a first shape and a second column whose uppermost plane has a second shape. N (N is a natural number equal to more than 1) first columns and N second columns are alternately arranged in a first direction different from the second direction.

Abstract: A semiconductor memory device includes a cell string with a plurality of selection transistors, a plurality of dummy transistors and a plurality of memory cell transistors coupled in series therein and a pass transistor (TR) unit with a plurality of pass transistors that transmit a plurality of driving signals to the cell string. The pass TR unit includes a plurality of first pass transistors transmitting a first driving signal with a first level voltage, among the plurality of driving signals, to the plurality of selection transistors, respectively, and a plurality of second pass transistors transmitting a second driving signal with a second level voltage that is higher than the first level voltage, among the plurality of driving signals, to a plurality of dummy transistors, respectively. Each of the second pass transistors has a larger channel area than each of the first pass transistors.

Abstract: A semiconductor memory device includes an electrode structure, a plurality of channel posts, and at least one gate separation layer. The electrode structure includes insulating interlayers and gate conductive layers which are alternately stacked. The channel posts are formed through the electrode structure. The gate separation layer is formed between the channel posts. The gate separation layer separates an uppermost gate conductive layer among the gate conductive layers. Each channel post among the channel posts adjacent to the gate separation layer has a gibbous moon shape in a planar view. The semiconductor memory device further includes a slit structure arranged at both sides of the gate separation layer. The slit structure is formed through the electrode structure. Each channel post among the channel posts adjacent to the slit structure has a gibbous moon shape in the planar view.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group, the upper gate stack structure; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

Abstract: A semiconductor manufacturing apparatus includes a loadlock module including a loadlock chamber in which a substrate container is received, wherein the loadlock module is configured to switch an internal pressure of the loadlock chamber between atmospheric pressure and a vacuum; and a transfer module configured to transfer a substrate between the substrate container received in the loadlock chamber and a process module for performing a semiconductor manufacturing process on the substrate, wherein the loadlock module includes a purge gas supply unit configured to supply a purge gas into the substrate container through a gas supply line connected to the substrate container; and an exhaust unit configured to discharge a gas in the substrate container through an exhaust line connected to the substrate container.

Abstract: A semiconductor manufacturing apparatus includes a loadlock module including a loadlock chamber in which a substrate container is received, wherein the loadlock module is configured to switch an internal pressure of the loadlock chamber between atmospheric pressure and a vacuum; and a transfer module configured to transfer a substrate between the substrate container received in the loadlock chamber and a process module for performing a semiconductor manufacturing process on the substrate, wherein the loadlock module includes a purge gas supply unit configured to supply a purge gas into the substrate container through a gas supply line connected to the substrate container; and an exhaust unit configured to discharge a gas in the substrate container through an exhaust line connected to the substrate container.

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.