Abstract: Disclosed is a semiconductor device, including: a vertical channel layer formed on a semiconductor substrate; first stack conductive layers stacked on the semiconductor substrate at a predetermined interval to surround one side surface of the vertical channel layer; second stack conductive layers stacked on the semiconductor substrate at the predetermined interval to surround the other side surface of the vertical channel layer; a first charge storage layer disposed between the vertical channel layer and the first stack conductive layers; and a second charge storage layer disposed between the vertical channel layer and the second stack conductive layers.

Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.

Abstract: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.

Abstract: A semiconductor device according to an embodiment may include cell strings including a plurality of memory cells coupled between bit lines and a source line and coupled to word lines, a peripheral circuit suitable for programming selected memory cells coupled to a selected word line among the word lines by applying a program voltage to the selected word line, and applying one or more pass voltages to unselected word lines, and a control circuit suitable for controlling the peripheral circuit to temporarily float the unselected word lines while the selected memory cells are programmed.

Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.

Abstract: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.

Abstract: A method of manufacturing a semiconductor memory device includes forming a first attached layer on a substrate, forming a stack layer on the first attached layer, separating the stack layer and the first attached layer from each other, forming vertical holes by performing a first etch process on the stack layer in a direction from bottom to top, removing the first attached layer, attaching the stack layer in which the vertical holes are formed to the substrate, and performing a second etch process so that each of the vertical holes has a uniform width.

Abstract: A semiconductor memory device includes a memory cell array configured to store data; peripheral circuits configured to perform program verifying operation, read operation, and erase verifying operation on the memory cell array; and a control circuit configured to control the peripheral circuits, wherein the control circuit is configured to control the peripheral circuits to set a bit line voltage in the program verifying operation to have a higher level than a bit line voltage in the read operation, and a bit line voltage in the erase verifying operation to have a lower level than the bit line voltage in the read operation.

Abstract: Provided are a non-volatile memory device and a method for erasing the non-volatile memory device having vertical channel layers formed with different widths varying by height and a plurality of memory cells stacked along the vertical channel layers, the method including increasing potentials of the vertical channel layers, and when potentials of word lines connected to the memory cells are increased, erasing the memory cells while lowering the potentials of the word lines beginning from a word line positioned in an area in which a width of the vertical channel layer is wide to a word line positioned in an area in which the width of the vertical channel layer is narrow.

Abstract: Provided are a non-volatile memory device and a method for erasing the non-volatile memory device having vertical channel layers formed with different widths varying by height and a plurality of memory cells stacked along the vertical channel layers, the method including increasing potentials of the vertical channel layers, and when potentials of word lines connected to the memory cells are increased, erasing the memory cells while lowering the potentials of the word lines beginning from a word line positioned in an area in which a width of the vertical channel layer is wide to a word line positioned in an area in which the width of the vertical channel layer is narrow.

Abstract: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.

Abstract: The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling.

Abstract: A semiconductor memory device includes a memory cell array configured to store data; peripheral circuits configured to perform program verifying operation, read operation, and erase verifying operation on the memory cell array; and a control circuit configured to control the peripheral circuits, wherein the control circuit is configured to control the peripheral circuits to set a bit line voltage in the program verifying operation to have a higher level than a bit line voltage in the read operation, and a bit line voltage in the erase verifying operation to have a lower level than the bit line voltage in the read operation.

Abstract: The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling.

Abstract: A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole.

Abstract: The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling.

Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.

Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor device includes insulation patterns and cell word lines alternately stacked on a substrate. A cell channel layer is formed through the insulation patterns and the cell word lines. A select channel layer is connected to the cell channel layer, and the select channel layer has a resistance higher than a resistance of the cell channel layer. A select line surrounds the select channel layer.

Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor device includes insulation patterns and cell word lines alternately stacked on a substrate. A cell channel layer is formed through the insulation patterns and the cell word lines. A select channel layer is connected to the cell channel layer, and the select channel layer has a resistance higher than a resistance of the cell channel layer. A select line surrounds the select channel layer.

Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.