Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

Abstract: An apparatus for attaching a pad on or to an edge ring includes a chamber defining a space for attaching a pad on or to an edge ring, a pad support within the chamber and supporting the pad thereon, an edge ring support within the chamber and facing the pad support, the edge ring support securing the edge ring thereon, a driving system connected to at least one of the pad support and the edge ring support and configured to move the edge ring support relative to the pad support, and a vacuum exhaust system configured to create a vacuum atmosphere within the chamber.

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

Abstract: A semiconductor manufacturing apparatus includes a loadlock module including a loadlock chamber in which a substrate container is received, wherein the loadlock module is configured to switch an internal pressure of the loadlock chamber between atmospheric pressure and a vacuum; and a transfer module configured to transfer a substrate between the substrate container received in the loadlock chamber and a process module for performing a semiconductor manufacturing process on the substrate, wherein the loadlock module includes a purge gas supply unit configured to supply a purge gas into the substrate container through a gas supply line connected to the substrate container; and an exhaust unit configured to discharge a gas in the substrate container through an exhaust line connected to the substrate container.

Abstract: Automated secure document and text communication. Secure messages using metadata to transmit hidden encryption keys. Cloud-based collaboration on always-encrypted documents and metadata; cloud-based collaboration on documents and metadata using virtual machines. Maintaining a distributed log for message path tracing, coupled to the message and securely encrypted, even when the message is securely encrypted. Secure message communication over a multi-hop path, that can alter encryption at each hop, adjust security measures at each hop, and include and log biometric sensors at each hop. Secure message communication, using media that can be manipulated by cameras, fax machines, photocopiers, printers, scanners, smart phones, or variants thereof. Free and substantially noiseless conversion of messages between digital and physical form. Secure message communication using multi-media to ensure non-interception and lack of machine readability if intercepted.

Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.

Abstract: An apparatus for calculating a filling time in an automatic transmission and a method thereof are disclosed. The apparatus includes an oil temperature detection unit for detecting an oil temperature of a transmission oil, a control duty input unit for receiving a control duty for controlling a solenoid valve that discharges or fills the transmission oil supplied from an oil pump from or to an oil flow path corresponding to a gear shifting stage to form a hydraulic pressure, a storage unit for storing a filling time table in which a relationship between a remaining flow and a filling time according to the oil temperature is mapped, and a calculation control unit for receiving the control duty of the solenoid valve from the control duty input unit to calculate the remaining flow on the basis of a variation interval of the remaining flow and an elapsed time, and calculating the filling time depending on the filling time table stored in the storage unit on the basis of the remaining flow.

Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.

Abstract: A semiconductor device may include first conductive patterns and first interlayer insulating layers. Each of the first conductive patterns may include a first pad pattern extending in a first direction and first line patterns extending from the first pad pattern in a second direction crossing the first direction, widths of the first line patterns increasing as a distance from the first pad pattern decreases. The first conductive patterns and the first interlayer insulating layers may be stacked on top of each other.

Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

Abstract: An apparatus for calculating a filling time in an automatic transmission and a method thereof are disclosed. The apparatus includes an oil temperature detection unit for detecting an oil temperature of a transmission oil, a control duty input unit for receiving a control duty for controlling a solenoid valve that discharges or fills the transmission oil supplied from an oil pump from or to an oil flow path corresponding to a gear shifting stage to form a hydraulic pressure, a storage unit for storing a filling time table in which a relationship between a remaining flow and a filling time according to the oil temperature is mapped, and a calculation control unit for receiving the control duty of the solenoid valve from the control duty input unit to calculate the remaining flow on the basis of a variation interval of the remaining flow and an elapsed time, and calculating the filling time depending on the filling time table stored in the storage unit on the basis of the remaining flow.

Abstract: A semiconductor device may include first conductive patterns and first interlayer insulating layers. Each of the first conductive patterns may include a first pad pattern extending in a first direction and first line patterns extending from the first pad pattern in a second direction crossing the first direction, widths of the first line patterns increasing as a distance from the first pad pattern decreases. The first conductive patterns and the first interlayer insulating layers may be stacked on top of each other.

Abstract: A nonvolatile memory device may include a plurality of memory blocks each including a drain select line, word lines and a source select line, and a pass transistor stage including a plurality of pass transistors formed in series in an active region and suitable for transferring word line voltages to a memory block selected among the memory blocks, in response to a block select signal, wherein the pass transistors each share a drain with a first adjacent pass transistor at one side while sharing a source with a second adjacent pass transistor at the other, and wherein a pair of pass transistors which share the source transfer word line driving signal form drains thereof to a pair of word lines which are included in different memory blocks among the memory blocks, through the source.

Abstract: Disclosed is a semiconductor device, including: a memory block including a plurality of memory strings, each of the memory strings including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, memory cells coupled to the drain select transistor and the source select transistor, and dummy memory cells coupled to the drain select transistor and the memory cell; and an operation circuit configured to perform a program operation on the memory cells. The operation circuit generates operation voltages applied to the dummy memory cells so that electric charges are generated by a band to band tunneling effect in the dummy memory cell adjacent to the drain select transistor during the program operation.

Abstract: A semiconductor memory device includes a plurality of memory cells connected to a plurality of word lines; a peripheral circuit suitable for applying a program pulse to at least one of the word lines, performing a program verification operation to the plurality of memory cells by using a first program verification voltage; and a control logic suitable for controlling the peripheral circuit to repeat the applying of the program pulse and the performing the program verification operation until program verification passes by increasing a level of the program pulse by an amount of a step voltage at each repetition, wherein a size of the step voltage decreases at each repetition.

Abstract: A semiconductor memory device includes a plurality of memory cells connected to a plurality of word lines; a peripheral circuit suitable for applying a program pulse to at least one of the word lines, performing a program verification operation to the plurality of memory cells by using a first program verification voltage; and a control logic suitable for controlling the peripheral circuit to repeat the applying of the program pulse and the performing the program verification operation until program verification passes by increasing a level of the program pulse by an amount of a step voltage at each repetition, wherein a size of the step voltage decreases at each repetition.

Abstract: The present disclosure provides a semiconductor device with a structural stability. The semiconductor device includes a stack of vertical alterations of conductive layers and insulating layers; supports passing through the stack, each of the supports having a cross-section of an equilateral polygon, the supports being equidistantly arranged in a first direction and a second direction, the first and second directions crossing each other; and contact plugs electrically coupled respectively to the conductive layers, each of the contact plugs being disposed between at least two adjacent supports of the supports.

Abstract: Disclosed is a semiconductor device, including: a memory block including a plurality of memory strings, each of the memory strings including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, memory cells coupled to the drain select transistor and the source select transistor, and dummy memory cells coupled to the drain select transistor and the memory cell; and an operation circuit configured to perform a program operation on the memory cells. The operation circuit generates operation voltages applied to the dummy memory cells so that electric charges are generated by a band to band tunneling effect in the dummy memory cell adjacent to the drain select transistor during the program operation.

Abstract: Disclosed is a semiconductor device, including: a vertical channel layer formed on a semiconductor substrate; first stack conductive layers stacked on the semiconductor substrate at a predetermined interval to surround one side surface of the vertical channel layer; second stack conductive layers stacked on the semiconductor substrate at the predetermined interval to surround the other side surface of the vertical channel layer; a first charge storage layer disposed between the vertical channel layer and the first stack conductive layers; and a second charge storage layer disposed between the vertical channel layer and the second stack conductive layers.