Patents by Inventor Suresh Venkatesan

Suresh Venkatesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11921156
    Abstract: A structure and method for the wafer level testing of interposer-based photonic integrated circuits is described that includes the formation of an upturned mirror structure and the method of utilizing the interposer-based mirror structure for electrical and optical testing of optoelectrical circuits that include emitting components such as lasers, detecting components such as photodetectors, and both emitting and detecting components. Electrical activation of the optoelectrical emitting or sending devices and the subsequent detection and measurement of the optical signals in detecting or receiving devices provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 5, 2024
    Inventors: Lucas Soldano, Jing Yang, Yong Meng Lee, Suresh Venkatesan
  • Patent number: 11906798
    Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: February 20, 2024
    Assignee: POET Technologies, Inc.
    Inventors: Yee Loy Lam, Suresh Venkatesan, Long Cheng Koh
  • Publication number: 20240004148
    Abstract: A structure and method for the formation of a reflector structure having three-dimensional surface curvature is disclosed. Beam narrowing upon reflection from the three-dimensionally curved surface in embodiments can provide improved coupling efficiency in addition to the directional change provided by the reflector.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 4, 2024
    Inventors: Lucas Soldano, Jing Yang, Yong Meng Lee, Suresh Venkatesan
  • Publication number: 20240004147
    Abstract: A structure and method for the formation of a reflector structure having three-dimensional surface curvature is disclosed. Beam narrowing upon reflection from the three-dimensionally curved surface in embodiments can provide improved coupling efficiency in addition to the directional change provided by the reflector.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 4, 2024
    Inventors: Lucas Soldano, Jing Yang, Yong Meng Lee, Suresh Venkatesan
  • Publication number: 20230384516
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Application
    Filed: March 27, 2023
    Publication date: November 30, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Publication number: 20230384515
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Application
    Filed: March 6, 2023
    Publication date: November 30, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Publication number: 20230333333
    Abstract: Alignment aid structures and the method of formation of these structures on an interposer comprised of a planar waveguide layer and a base structure, facilitate the alignment of the optical axes of optical and optoelectrical devices formed from and mounted to the interposer. Alignment aids formed from a common hard mask on the planar waveguide layer of the interposer structure include vertical and lateral alignment structures and fiducials. Optical losses for signals propagating in interposer-based photonic integrated circuits are reduced with effective alignment structures and methods.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventor: Suresh Venkatesan
  • Publication number: 20230258884
    Abstract: A structure and method of formation of a buried heterostructure laser die with alignment aids wherein the alignment aids include lateral and vertical structures formed on the die. Lateral alignment aids are formed using a same mask layer as the ridge structure of the laser and provide fiducials that are formed in reference to the ridge structure. Vertical alignment aids, and vertical protrusions of the lateral alignment aids are formed using etch stop layers positioned in the buried heterostructure laser layer structure.
    Type: Application
    Filed: February 14, 2023
    Publication date: August 17, 2023
    Inventor: Suresh Venkatesan
  • Publication number: 20230228953
    Abstract: An interposer PIC structure having a fanout waveguide structure is described for which the patterned planar waveguides of the fanout waveguide structure is formed from a same hard mask patterning step comprising a patterned area for a lateral alignment aid used to align the linearly configured cores of a multicore fiber with a terminal end of the fanout waveguide structure. Areas of the same patterned hard mask may optionally include one or more fiducials and one or more alignment pillars for aligning mounted devices onto the PIC structure. Interposer PIC assemblies are described comprising the interposer PIC structure, multicore fibers having linearly configured arrays of cores, and devices mounted or otherwise formed on the interposer PIC structure. Methods of forming the interposer PIC structures and assemblies are also disclosed.
    Type: Application
    Filed: November 21, 2022
    Publication date: July 20, 2023
    Inventors: Suresh Venkatesan, Jing Yang, Lucas Soldano
  • Patent number: 11686906
    Abstract: Alignment aid structures and the method of formation of these structures on an interposer comprised of a planar waveguide layer and a base structure, facilitate the alignment of the optical axes of optical and optoelectrical devices formed from and mounted to the interposer. Alignment aids formed from a common hard mask on the planar waveguide layer of the interposer structure include vertical and lateral alignment structures and fiducials. Optical losses for signals propagating in interposer-based photonic integrated circuits are reduced with effective alignment structures and methods.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: June 27, 2023
    Inventor: Suresh Venkatesan
  • Publication number: 20230176303
    Abstract: Embodiments of alignment structures are disclosed that enable the alignment of a fiber attach unit (FAU) and the optical fibers contained therein to optical components on optical interposers or substrates on which photonic integrated circuits (PICs) are formed. Alignment of the optical fibers is enabled without the requirement for powering of the active optoelectrical devices in the PIC, but rather use an external testing apparatus to provide one or more optical signals to facilitate alignment. Methods for alignment using embodiments of the alignment structure is also disclosed.
    Type: Application
    Filed: October 9, 2022
    Publication date: June 8, 2023
    Inventors: Suresh Venkatesan, Jing Yang, Lucas Soldano
  • Patent number: 11670908
    Abstract: The invention described herein pertains to the structure and formation of an optical device that includes a planar laser and a waveguide. The planar laser has a large lateral QW-containing layer and a tapered section in a transition portion of the device structure that enable low diode leakage currents and facilitate transition of the optical signal from the laser to a transition waveguide, and in some embodiments, to a dilute waveguide.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 6, 2023
    Assignee: POET Technologies, Inc.
    Inventor: Suresh Venkatesan
  • Publication number: 20230152519
    Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.
    Type: Application
    Filed: January 3, 2023
    Publication date: May 18, 2023
    Inventors: William Ring, Miroslaw Florjanczyk, Suresh Venkatesan
  • Publication number: 20230130757
    Abstract: A structure and method for providing alignment aids that are co-fabricated with the optical emission output from a laser pedestal are described. In embodiments, the alignment aids are formed using processes and masking layers that produce a ridge waveguide laser structure. The use of same masking processes for the laser and the alignment aids provides lithographic level precision in the positioning of the alignment aids in relation to the optical output from the laser device. Optoelectrical die formed with the alignment aids may be used with complementary interposer structures to enable alignment of optical output from lasers formed on the optoelectrical die with optical devices on the interposer.
    Type: Application
    Filed: May 24, 2022
    Publication date: April 27, 2023
    Inventor: Suresh Venkatesan
  • Patent number: 11614584
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 28, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 11598918
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 7, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 11592621
    Abstract: The invention described herein pertains to the structure and formation of dual core waveguide structures and to the formation of optical devices including spot size converters from these dual core waveguide structure for the receiving and routing of optical signals on substrates, interposers, and sub-mount assemblies.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 28, 2023
    Inventors: Suresh Venkatesan, Miroslaw Florjanczyk, Trevor Hall, Peng Liu, Jing Yang
  • Patent number: 11585984
    Abstract: The invention described herein pertains to the structure and formation of dual core waveguide structures and to the formation of optical devices including spot size converters from these dual core waveguide structure for the receiving and routing of optical signals on substrates, interposers, and sub-mount assemblies.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 21, 2023
    Inventors: Suresh Venkatesan, Miroslaw Florjanczyk, Trevor Hall, Peng Liu, Jing Yang
  • Publication number: 20230038028
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 9, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 11573372
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 7, 2023
    Inventors: William Ring, Suresh Venkatesan