Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.

Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Abstract: The invention described herein pertains to the structure and formation of dual core waveguide structures and to the formation of optical devices including spot size converters from these dual core waveguide structure for the receiving and routing of optical signals on substrates, interposers, and sub-mount assemblies.

Abstract: The invention described herein pertains to the structure and formation of dual core waveguide structures and to the formation of optical devices including spot size converters from these dual core waveguide structure for the receiving and routing of optical signals on substrates, interposers, and sub-mount assemblies.

Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.

Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Abstract: A vertical cavity surface emitting laser (VCSEL) is formed on a substrate. The VCSEL includes a layer structure and one or more distributed Bragg reflector (DBR) mirrors formed on at least one of the layer structure or the substrate. The layer structure generates an optical signal at a first wavelength based on a control current received from a transistor that is formed on the substrate. Rare earth ions (REIs) are deposited in the one or more DBR mirrors such that the one or more DBR mirrors receive the optical signal at the first wavelength and generate the optical signal at a second wavelength.

Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.

Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Abstract: Disclosed is an automation testing platform for facilitating automatic testing of an Information technology (IT) enabled application. A data capturing module captures one or more objects and at least one action performed on the one or more objects. A re-usable test script creation module creates a plurality of re-usable test scripts based on the one or more objects and the at least one action. A keyword assignment module assigns a unique keyword to each re-usable test scripts. A mapping module stores a mapping table comprising mapping of the unique keyword and each of the plurality of re-usable test scripts. A keyword selection module selects the unique keyword, corresponds to a re-usable test script of the plurality of re-usable test scripts, from the mapping table. A test script execution module executes the re-usable test script thereby facilitating automatic testing of the specific use-case pertaining to the IT enabled application.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.