Patents by Inventor Tadahiro Ishizaka

Tadahiro Ishizaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9313895
    Abstract: There is provided a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess, which is formed in a predetermined pattern in a Si-containing film of a substrate. The Cu wiring forming method includes forming a Mn film, which becomes a self-aligned barrier film by reaction with an underlying base, at least on a surface of the recess by chemical vapor deposition, forming a Cu film by a physical vapor deposition to fill the recess with the Cu film, and forming a Cu wiring in the recess by polishing the entire surface of the substrate by a chemical mechanical polishing.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 12, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Kenji Suzuki, Atsushi Shimada
  • Publication number: 20150332961
    Abstract: Cu wiring fabrication method for fabricating Cu wiring with respect to substrate having interlayer dielectric film having trench formed thereon, includes: forming barrier film on surface of the trench; forming Ru film on surface of the barrier film by CVD; burying the trench by forming Cu film or Cu alloy film on the Ru film; forming Cu film or Cu alloy film at corners of bottom of the trench while re-sputtering the formed Cu film or Cu alloy film in a condition where first formed Cu film or Cu alloy film re-sputtered by an ion action of the plasma generation gas; and subsequently burying the Cu film or the Cu alloy film in the trench in condition where the Cu film or the Cu alloy film is formed on field portion of the substrate, and reflows in the trench by an ion action of the plasma generation gas.
    Type: Application
    Filed: May 1, 2015
    Publication date: November 19, 2015
    Inventors: Tadahiro ISHIZAKA, Tatsuo HIRASAWA, Takashi SAKUMA, Osamu YOKOYAMA
  • Publication number: 20150325432
    Abstract: A film forming method in which in a state in which a target substrate is loaded on a loading table body of a loading table installed in a processing container and an interior of the processing container is evacuated, a film forming material gas is supplied into the processing container while heating the target substrate with a heater installed in the loading table body, to be thermally decomposed or reacted on a surface of the target substrate to form a predetermined film on the target substrate, includes introducing a heat transfer gas containing an H2 gas or an He gas into the processing container to transfer heat of the loading table body to a radially outer side of the loading table body, before the film forming material gas is supplied.
    Type: Application
    Filed: April 28, 2015
    Publication date: November 12, 2015
    Inventor: Tadahiro ISHIZAKA
  • Publication number: 20150262872
    Abstract: A method of forming a copper wiring buried in a recess portion of a predetermined pattern formed in an interlayer insulation layer of a substrate is disclosed. The method includes: forming a manganese oxide film at least on a surface of the recess portion, the manganese oxide film serving as a self-aligned barrier film through reaction with the interlayer insulation layer; performing hydrogen radical treatment with respect to a surface of the manganese oxide film; placing a metal more active than ruthenium on the surface of the manganese oxide film after the hydrogen radical treatment; forming a ruthenium film on the surface where the metal more active than ruthenium is present; and forming a copper film on the ruthenium film by physical vapor deposition (PVD) to bury the copper film in the recess portion.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 17, 2015
    Inventors: Tadahiro ISHIZAKA, Takashi SAKUMA, Osamu YOKOYAMA, Kenji MATSUMOTO, Peng CHANG, Hiroyuki NAGAI
  • Publication number: 20150240344
    Abstract: A ruthenium film forming method includes: placing a target substrate in a processing container; supplying ruthenium carbonyl gas together with CO gas as a carrier gas into the processing container, the ruthenium carbonyl gas being generated from solid-state ruthenium carbonyl; supplying additional CO gas into the processing container; and forming a ruthenium film on the target substrate by decomposing the ruthenium carbonyl gas.
    Type: Application
    Filed: February 16, 2015
    Publication date: August 27, 2015
    Inventors: Tadahiro ISHIZAKA, Takashi SAKUMA, Tatsuo HIRASAWA
  • Publication number: 20150221550
    Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.
    Type: Application
    Filed: February 3, 2015
    Publication date: August 6, 2015
    Inventors: Kai-Hung Yu, Toshio Hasegawa, Tadahiro Ishizaka, Manabu Oie, Fumitaka Amano, Steven Consiglio, Cory Wajda, Kaoru Maekawa, Gert J. Leusink
  • Patent number: 9101067
    Abstract: In a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess which is formed in a substrate in a predetermined pattern, a barrier film formed of a TaAlN film is formed at least on the surface of the recess by thermal ALD or thermal CVD. Then a Cu film is formed to fill the recess with the Cu film. Further, the Cu wiring is formed in the recess by polishing the entire surface of the substrate by CMP.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 4, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Toshio Hasegawa
  • Patent number: 9064690
    Abstract: A Cu wiring forming method forms Cu wiring in a recess of a predetermined pattern including a trench formed in an insulating film on a substrate surface. The method includes: forming a barrier film at least on a surface of the recess; forming a Cu film by PVD to fill the recess with the Cu film; forming an additional layer on the Cu film; polishing an entire surface by CMP to form the Cu wiring in the recess; forming a metal cap including a manganese oxide film on an entire surface including the insulating film and the Cu wiring of the substrate after performing the CMP polishing; and forming a dielectric cap on the metal cap.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: June 23, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Atsushi Gomi, Kenji Suzuki, Tatsuo Hatano, Hiroyuki Toshima, Yasushi Mizusawa
  • Publication number: 20150170963
    Abstract: A semiconductor device manufacturing method includes: performing nitrogen plasma processing on an interlayer insulating film made of a fluorine containing carbon film having a recess formed in a surface thereof in a predetermined pattern; forming a Ru film directly on the fluorine containing carbon film subjected to the nitrogen plasma processing. The semiconductor device manufacturing method further includes filling a Cu film in the recess to form a Cu wiring.
    Type: Application
    Filed: December 9, 2014
    Publication date: June 18, 2015
    Inventors: Tadahiro ISHIZAKA, Kotaro MIYATANI, Takuya KUROTORI
  • Patent number: 8999841
    Abstract: A semiconductor device manufacturing method includes: modifying a surface of a burying recess, of which surface is hydrophobic and which is formed in a dielectric film, to a hydrophilic state by supplying a plasma containing H ions and H radicals or a plasma containing NHx (x being 1, 2 or 3) ions and NHx radicals to the dielectric film formed on a substrate and containing silicon, carbon, hydrogen and oxygen, a bottom portion of the burying recess being exposed with a lower conductive layer; and directly forming an adhesion film formed of a Ru film on the hydrophilic surface of the recess. The method further includes burying copper forming a conductive path in the recess.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: April 7, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Atsushi Gomi, Kenzi Suzuki, Tatsuo Hatano, Yasushi Mizusawa
  • Patent number: 8974868
    Abstract: A method for processing a substrate includes disposing the substrate in a deposition chamber configured to perform a deposition process and depositing a film on the substrate using the deposition process. The substrate having the film thereon is then transferred from the deposition chamber into a treatment chamber and a plasma cleaning process is performed on the substrate in the treatment chamber. Further processing of the substrate is performed after the plasma cleaning process.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Audunn Ludviksson
  • Publication number: 20150056385
    Abstract: In a Cu wiring structure forming method, a barrier film serving as a Cu diffusion barrier is formed at least on a surface of a recess in a first insulating film formed on a substrate, and the recess is filled with an Al-containing Cu film. A Cu wiring is formed from the Al-containing Cu film, and a cap layer including a Ru film is formed on the Cu wiring. Further, an interface layer containing a Ru—Al alloy is formed at an interface between the Cu wiring and the cap layer by heat generated in forming the cap layer or by a heat treatment performed after forming the cap layer. A second insulating film is formed on the cap layer.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 26, 2015
    Inventors: Tadahiro ISHIZAKA, Kenji SUZUKI
  • Publication number: 20150004784
    Abstract: Provided is a method of forming a copper (Cu) wiring in a recess formed to have a predetermined pattern in an insulating film formed on a surface of a substrate. The method includes: forming a barrier film at least on a surface of the recess, the barrier film serving as a barrier for blocking diffusion of Cu; forming a Ru film on the barrier film by Chemical Mechanical Deposition (CVD); forming a Cu alloy film on the Ru film by Physical Vapor Deposition (PVD) to bury the recess; forming a Cu wiring using the Cu alloy film buried in the recess; and forming a dielectric film on the Cu wiring.
    Type: Application
    Filed: June 26, 2014
    Publication date: January 1, 2015
    Inventors: Osamu YOKOYAMA, Cheonsoo HAN, Takashi SAKUMA, Chiaki YASUMURO, Tatsuo HIRASAWA, Tadahiro ISHIZAKA, Kenji SUZUKI
  • Publication number: 20140377947
    Abstract: When a recess is formed in a SiCOH film, C is removed from the film to form a damage layer. If the damage layer is removed by hydrofluoric acid or the like, the surface becomes hydrophobic. By supplying a boron compound gas, a silicon compound gas or a gas containing trimethyl aluminum to the SiCOH film, B, Si or Al is adsorbed on the SiCOH film. These atoms bond with Ru and a Ru film is easily formed on the SiCOH film. The Ru film is formed using, for example, Ru3(CO)12 gas and CO gas. Copper is filled in the recess and an upper side wiring structure is formed by carrying out CMP processing.
    Type: Application
    Filed: January 24, 2013
    Publication date: December 25, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Atsushi Gomi, Kenji Suzuki, Tatsuo Hatano, Yasushi Mizusawa
  • Patent number: 8859422
    Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding Cu in the trench or hole by forming a Cu film on the Ru film using PVD while annealing the substrate such that migration of copper into the trench or hole occurs.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: October 14, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Atsushi Gomi, Takara Kato, Osamu Yokoyama, Takashi Sakuma, Chiaki Yasumuro, Hiroyuki Toshima, Tatsuo Hatano, Yasushi Mizusawa, Masamichi Hara, Kenzi Suzuki
  • Publication number: 20140287163
    Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding Cu in the trench or hole by forming a Cu film on the Ru film using PVD while annealing the substrate such that migration of copper into the trench or hole occurs.
    Type: Application
    Filed: June 6, 2014
    Publication date: September 25, 2014
    Inventors: Tadahiro ISHIZAKA, Atsushi GOMI, Takara FUKUSHIMA, Osamu YOKOYAMA, Takashi SAKUMA, Chiaki YASUMURO, Hiroyuki TOSHIMA, Tatsuo HATANO, Yasushi MIZUSAWA, Masamichi HARA, Kenzi SUZUKI
  • Publication number: 20140175046
    Abstract: In a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess which is formed in a substrate in a predetermined pattern, a barrier film formed of a TaAlN film is formed at least on the surface of the recess by thermal ALD or thermal CVD. Then a Cu film is formed to fill the recess with the Cu film. Further, the Cu wiring is formed in the recess by polishing the entire surface of the substrate by CMP.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 26, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Tadahiro ISHIZAKA, Toshio HASEGAWA
  • Publication number: 20140161992
    Abstract: There is provided a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess, which is formed in a predetermined pattern in a Si-containing film of a substrate. The Cu wiring forming method includes forming a Mn film, which becomes a self-aligned barrier film by reaction with an underlying base, at least on a surface of the recess by chemical vapor deposition, forming a Cu film by a physical vapor deposition to fill the recess with the Cu film, and forming a Cu wiring in the recess by polishing the entire surface of the substrate by a chemical mechanical polishing.
    Type: Application
    Filed: December 5, 2013
    Publication date: June 12, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Tadahiro ISHIZAKA, Kenji SUZUKI, Atsushi SHIMADA
  • Patent number: 8716132
    Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, exposing the patterned substrate to a process gas comprising a metal-containing precursor, and irradiating the patterned substrate with electromagnetic radiation, where selective metal-containing cap layer formation on the Cu metal surfaces is facilitated by the electromagnetic radiation. In some embodiments, the method further includes pre-treating the patterned substrate with additional electromagnetic radiation and optionally a cleaning gas prior to forming the metal-containing cap layer.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: May 6, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Shigeru Mizuno
  • Publication number: 20140045329
    Abstract: A Cu wiring forming method forms Cu wiring in a recess of a predetermined pattern including a trench formed in an insulating film on a substrate surface. The method includes: forming a barrier film at least on a surface of the recess; forming a Cu film by PVD to fill the recess with the Cu film; forming an additional layer on the Cu film; polishing an entire surface by CMP to form the Cu wiring in the recess; forming a metal cap including a manganese oxide film on an entire surface including the insulating film and the Cu wiring of the substrate after performing the CMP polishing; and forming a dielectric cap on the metal cap.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 13, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro ISHIZAKA, Atsushi Gomi, Kenji Suzuki, Tatsuo Hatano, Hiroyuki Toshima, Yasushi Mizusawa