Patents by Inventor Tadahiro Ishizaka

Tadahiro Ishizaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140030886
    Abstract: A copper (Cu) wiring forming method includes forming a barrier film on the entire surface of a wafer which has a trench, forming a ruthenium (Ru) film on the barrier film, and filling the trench by forming a pure copper film on the ruthenium film by a physical vapor deposition (PVD). The method further includes forming a copper alloy film on the pure copper film by the PVD, forming a copper wiring by polishing the entire surface by a chemical mechanical polishing, forming a cap layer made of a dielectric material on the copper wiring, and segregating an alloy component included in the copper alloy film in a region including a portion corresponding an interface between the copper wiring and the cap layer.
    Type: Application
    Filed: September 30, 2013
    Publication date: January 30, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Takara FUKUSHIMA, Tadahiro Ishizaka, Atsushi Gomi, Tatsuo Hatano, Yasushi Mizusawa
  • Publication number: 20130252417
    Abstract: A thin film forming method in which a thin film is formed on a surface of a target object to be processed to fill a recess formed in the surface of the target object includes the steps of forming a metal layer for filling on the surface of the target object to fill the recess formed in the surface of the target object and forming a metal film for preventing diffusion on an entire surface of the target object to cover the metal layer for filling. The thin film forming method further includes the step of annealing the target object having the metal film for preventing diffusion formed thereon.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 26, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro ISHIZAKA, Jonathan Rullan, Osamu Yokoyama, Atsushi Gomi, Chiaki Yasumuro, Takara Kato, Tatsuo Hatano, Hiroaki Kawasaki
  • Publication number: 20130237053
    Abstract: A film forming method which generates metal ions from a metal target with a plasma in a processing chamber and attracts the metal ions with a bias to deposit a metal thin film on a target object wherein trenches are formed. The method includes: generating metal ions from a target and attracting the metal ions into a target object with a bias to form a base film in a trench; ionizing a rare gas with the bias in a state where no metal ion is generated and attracting the generated ions into the target object to etch the base film; and plasma sputtering the target to generate metal ions and attracting the metal ions into the object with a high frequency power for bias to deposit a main film as a metal film, while reflowing the main film by heating.
    Type: Application
    Filed: September 26, 2011
    Publication date: September 12, 2013
    Applicant: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Takashi Sakuma, Tatsuo Hatano, Osamu Yokoyama, Atsushi Gomi, Chiaki Yasumuro, Toshihiko Fukushima, Hiroyuki Toshima, Masaya Kawamata, Yasushi Mizusawa, Takara Kato
  • Publication number: 20130203250
    Abstract: A semiconductor device manufacturing method includes: modifying a surface of a burying recess, of which surface is hydrophobic and which is formed in a dielectric film, to a hydrophilic state by supplying a plasma containing H ions and H radicals or a plasma containing NHx (x being 1, 2 or 3) ions and NHx radicals to the dielectric film formed on a substrate and containing silicon, carbon, hydrogen and oxygen, a bottom portion of the burying recess being exposed with a lower conductive layer; and directly forming an adhesion film formed of a Ru film on the hydrophilic surface of the recess. The method further includes burying copper forming a conductive path in the recess.
    Type: Application
    Filed: August 3, 2012
    Publication date: August 8, 2013
    Applicant: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Atsushi Gomi, Kenzi Suzuki, Tatsuo Hatano, Yasushi Mizusawa
  • Patent number: 8399353
    Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding copper in the trench or hole by forming a Cu film on the Ru film using PVD while heating the substrate such that migration of copper into the trench or hole occurs.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: March 19, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Atsushi Gomi, Takara Kato, Osamu Yokoyama, Takashi Sakuma, Chiaki Yasumuro, Hiroyuki Toshima, Tatsuo Hatano, Yasushi Mizusawa, Masamichi Hara
  • Patent number: 8372739
    Abstract: An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: February 12, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Satohiko Hoshino, Kuzuhiro Hamamoto, Shigeru Mizuno, Yasushi Mizusawa
  • Publication number: 20120315404
    Abstract: A method for vapor deposition on a substrate in a vapor deposition system having a process space separated from a transfer space. The method disposes a substrate in a process space of a processing system that is vacuum isolated from a transfer space of the processing system, processes the substrate at either of a first position or a second position in the process space while maintaining vacuum isolation from the transfer space by way of a movement accommodating sealing material, and deposits a material on the substrate at either the first position or the second position.
    Type: Application
    Filed: August 1, 2012
    Publication date: December 13, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yicheng LI, Tadahiro ISHIZAKA, Kaoru YAMAMOTO, Atsushi GOMI, Masamichi HARA, Toshiaki FUJISATO, Jacques FAGUET, Yasushi MIZUSAWA
  • Publication number: 20120247949
    Abstract: A film forming method includes depositing a metal thin film on a target substrate by generating an inductively coupled plasma in a processing chamber while introducing a plasma generating gas in the processing chamber with the substrate disposed on a placing table, by supplying DC power to a metal target from a DC power source, and by applying high-frequency bias to the placing table. A resputtering method includes resputtering the deposited metal thin film by stopping the generating of the inductively coupled plasma, by stopping the power supply from the DC power source, and by applying the high-frequency bias to the placing table while introducing the plasma generating gas in the processing chamber to form a capacitively coupled plasma in the processing chamber and by attracting ions of the plasma generating gas to the target substrate where the metal thin film is deposited.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 4, 2012
    Inventors: Takashi SAKUMA, Tadahiro Ishizaka, Tatsuo Hatano, Shiro Hayashi, Toshiaki Fujisato, Hiroyuki Yokohara, Hiroyuki Toshima
  • Publication number: 20120222782
    Abstract: In a Cu wiring forming method which is followed by a post-process including a treatment of a temperature of 500° C. or higher, an adhesion film made of a metal having a lattice spacing that differs from the lattice spacing of Cu by 10% or less is formed on a substrate having a trench and/or a hole in the surface such that the adhesion film is deposited on at least the bottom and side surfaces of the trench and/or hole. A Cu film is formed on the adhesion film to fill the trench and/or hole. An annealing process is performed on the substrate on which the Cu film has been formed at 350° C. or higher. The CU film is polished to leave only the part of the Cu film which corresponds to the trench and/or hole. A cap is formed on the polished Cu film to form a Cu wiring.
    Type: Application
    Filed: August 27, 2010
    Publication date: September 6, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Atsushi Gomi, Yasushi Mizusawa, Tatsuo Hatano, Osamu Yokoyama, Tadahiro Ishizaka, Chiaki Yasumuro, Takara Kato
  • Patent number: 8242019
    Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: August 14, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Shigeru Mizuno, Satohiko Hoshino, Hiroyuki Nagai, Yuki Chiba, Frank M. Cerio, Jr.
  • Publication number: 20120196052
    Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding Cu in the trench or hole by forming a Cu film on the Ru film using PVD while annealing the substrate such that migration of copper into the trench or hole occurs.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 2, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro ISHIZAKA, Atsushi GOMI, Takara KATO, Osamu YOKOYAMA, Takashi SAKUMA, Chiaki YASUMURO, Hiroyuki TOSHIMA, Tatsuo HATANO, Yasushi MIZUSAWA, Masamichi HARA, Kenzi SUZUKI
  • Publication number: 20120196437
    Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding copper in the trench or hole by forming a Cu film on the Ru film using PVD while heating the substrate such that migration of copper into the trench or hole occurs.
    Type: Application
    Filed: April 6, 2011
    Publication date: August 2, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro ISHIZAKA, Atsushi GOMI, Takara KATO, Osamu YOKOYAMA, Takashi SAKUMA, Chiaki YASUMURO, Hiroyuki TOSHIMA, Tatsuo HATANO, Yasushi MIZUSAWA, Masamichi HARA
  • Patent number: 8075698
    Abstract: A substrate processing unit comprises a processing vessel for receiving a substrate, a cleaning gas supply system for supplying cleaning gas to the processing vessel so as to clean the interior of the processing vessel, an exhauster for exhausting the processing vessel, an operating state detector for detecting the operating state of the exhauster, and an end point detector for detecting the end point of the cleaning on the basis of the detection result from the operating state detector.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: December 13, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Kannan, Tadahiro Ishizaka, Yasuhiko Kojima, Yasuhiro Oshima, Takashi Shigeoka
  • Patent number: 8058728
    Abstract: An interconnect structure is provided. The interconnect structure includes an interconnect opening formed within a dielectric material, a diffusion barrier on the dielectric material, where the diffusion barrier contains a compound from a thermal reaction between cobalt (Co) metal from at least a portion of a cobalt metal layer formed on the dielectric material and a dielectric reactant element from the dielectric material. The interconnect structure further includes a cobalt nitride adhesion layer in the interconnect opening, and a Cu metal fill in the interconnect opening, wherein the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal fill within the interconnect opening.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: November 15, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Shigeru Mizuno
  • Patent number: 8034406
    Abstract: A method and system are provided for integrated substrate processing in Cu metallization. The method includes providing a substrate in a vacuum processing tool containing a plurality of processing systems configured to process the substrate and a substrate transfer system configured to transfer the substrate under vacuum conditions between the plurality of processing systems, and performing an integrated deposition process on the substrate. The plurality of processing systems and the substrate transfer system maintain a base pressure of background gases at 6.8×10?8 Ton or lower, preferably 5×10?8 Torr or lower, during the integrated deposition process. According to one embodiment, the integrated process includes depositing a barrier metal layer on the substrate, and depositing a Cu layer on the barrier metal layer. According to another embodiment, the integrated process further includes depositing a Ru layer on the barrier metal layer, and depositing a Cu layer on the Ru layer.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: October 11, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Masamichi Hara, Yasushi Mizusawa
  • Patent number: 8026168
    Abstract: The method includes providing a substrate containing a dielectric layer having a recessed feature and forming a aluminum tantalum carbonitride barrier film over a surface of the recessed feature. The aluminum tantalum carbonitride barrier film is formed by depositing a plurality of tantalum carbonitride films, and depositing aluminum between each of the plurality of tantalum carbonitride films. One embodiment further comprises depositing a Ru film on the aluminum tantalum carbonitride barrier film, depositing a Cu seed layer on the Ru film, and filling the recessed feature with bulk Cu. A semiconductor device containing an aluminum tantalum carbonitride barrier film is described.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: September 27, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Shigeru Mizuno
  • Patent number: 7989353
    Abstract: Method for operating a processing system and refurbishing a ceramic substrate holder within a process chamber of the processing system are described. The method includes plasma processing one or more substrates on the ceramic substrate holder, where the processing causes erosion of a nitride material of the ceramic substrate holder. The method further includes refurbishing the ceramic substrate holder in-situ without a substrate residing on the ceramic substrate holder, where the refurbishing includes exposing the ceramic substrate holder to a plasma-excited nitrogen-containing gas in the process chamber to at least partially reverse the erosion of the nitride material.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: August 2, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Kentaro Asakura, Masanao Ando, Toshio Hasegawa
  • Patent number: 7977235
    Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, forming a patterned mask layer on the patterned substrate, where the patterned mask layer contains openings that expose the Cu metal surfaces. The method further includes depositing a metal-containing layer on the Cu metal surfaces, depositing an additional metal-containing layer on the patterned mask layer, and removing the patterned mask layer and the additional metal-containing layer from the patterned substrate to selectively form metal-containing cap layers on the Cu metal surfaces.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: July 12, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Tadahiro Ishizaka
  • Patent number: 7959985
    Abstract: A method for forming a modified TaC or TaCN film that may be utilized as a barrier film for Cu metallization. The method includes disposing a substrate in a process chamber of a plasma enhanced atomic layer deposition (PEALD) system configured to perform a PEALD process, depositing a TaC or TaCN film on the substrate using the PEALD process, and modifying the deposited TaC or TaCN film by exposing the deposited TaC or TaCN film to plasma excited hydrogen or atomic hydrogen or a combination thereof in order to remove carbon from at least the plasma exposed portion of the deposited TaCN film. The method further includes forming a metal film on the modified TaCN film, where the modified TaCN film provides stronger adhesion to the metal film than the deposited TaCN film. According to one embodiment, a TaCN film is deposited from alternating exposures of TAIMATA and plasma excited hydrogen.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: June 14, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Tsukasa Matsuda, Masamichi Hara, Jacques Faguet, Yasushi Mizusawa
  • Patent number: 7884012
    Abstract: A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and depositing a discontinuous Cu seed layer on the Ru metal film, where the Cu seed layer partially covers the Ru metal film in the recessed feature. The method further includes exposing the substrate to an oxidation source gas that oxidizes the Cu seed layer and the portion of the Ru metal film not covered by the Cu seed layer, heat-treating the oxidized Cu seed layer and the oxidized Ru metal film under high vacuum conditions or in the presence of an inert gas to activate the oxidized Ru metal film for Cu plating, and filling the recessed feature with bulk Cu metal.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 8, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kenji Suzuki, Tadahiro Ishizaka, Miho Jomen, Jonathan Rullan