Abstract: This invention relates to a positive photosensitive resin composition that includes a siloxane copolymer of two kinds of reactive silane compounds with specific structures wherein residual impurities such as unreacted monomers and catalysts are minimized, and a UV absorber including one or more kinds of phenol hydroxyl groups capable of crosslinking and an alkoxy group. Accordingly, the resin composition exhibits excellent performances such as sensitivity, resolution, and degree of planarization, and also has excellent weatherability and UV absorbance, thereby providing excellent panel reliability.

Abstract: The present disclosure relates to a photo-curable composition, a cured product thereof, and an optical member and a display device comprising same. The photo-curable composition has excellent low refractive index, light transmittance, and low haze characteristics by comprising a first olefinic monomer containing fluorine, a second olefinic monomer having an absolute viscosity of 7 cP or less at 25° C., a photo-polymerization initiator, and an amine compound.

Abstract: A coil component is provided. The coil component includes a body having fifth and sixth surfaces opposing each other, first and second surfaces respectively connecting the fifth and sixth surfaces of the body and opposing each other, and third and fourth surfaces respectively connecting the first and second surfaces of the body and opposing each other in one direction, a recess disposed in an edge between one of the first and second surfaces of the body and the sixth surface of the body, a coil portion disposed inside the body and exposed through the recess, and an external electrode including a connection portion disposed in the recess and connected to the coil portion, and a pad portion disposed on one surface of the body. A length of the pad portion in the one direction is greater than a length of the connection portion in the one direction.

Abstract: The present disclosure relates to an aluminum alloy-plated steel sheet having excellent workability and corrosion resistance and a method for manufacturing the same, and more particularly, to an aluminum alloy-plated steel sheet that prevents microcracks generated during hot forming and has excellent seizure resistance and corrosion resistance, and a method for manufacturing the same.

Abstract: The present disclosure relates to an aluminum alloy-plated steel sheet having excellent workability and corrosion resistance and a method for manufacturing the same, and more particularly, to an aluminum alloy-plated steel sheet preventing microcracks generated during hot forming and has excellent seizure resistance and corrosion resistance, and a method for manufacturing the same.

Abstract: An embodiment of the present invention provides a high strength hot-dip galvanized steel sheet having excellent plating adhesion and weldability and a method of manufacturing same, wherein: the steel sheet comprises a base steel sheet and a hot-dip galvanized layer formed on one surface or both surfaces of the base steel sheet, the base steel sheet comprising, in weight %, carbon (C): 0.1-0.3%, silicon (Si): 0.1-2.0%, aluminum (Al): 0.1-1.5%, manganese (Mn): 1.5-3.0%, and the balance being Fe and inevitable impurities, the sum of Si and Al satisfying 1.2-3.5%, the ratio (Al/Si) of Al and Si satisfying 0.5-2.0; the steel sheet comprises an internal oxidation layer with a thickness of 1-5 ?m directly below the surface of the base steel sheet; and the decarburization rate in a region from directly below the surface of the base steel sheet to 50 ?m is 50% or more.

Abstract: A planar type solid oxide fuel cell, and more particularly, a thin and light planar type solid oxide fuel cell omits a window frame and has a simplified a unit cell having a through hole through which fuel and air flow in/out a fuel electrode.

Abstract: An interconnect for a solid oxide fuel cell, its manufacturing method, and a solid oxide fuel cell including the same are provided.

Abstract: A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.

Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.

Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.

Abstract: Provided are a hot-dipped galvanized steel material and a method for manufacturing the same. The hot-dipped galvanized steel material comprises an iron substrate and a hot-dipped galvanizing layer formed on the iron substrate, wherein the hot-dipped galvanizing layer comprises, by wt %, 0.01 to 0.5% of Al, 0.01 to 1.5% of Mg, 0.05 to 1.5% of Mn, 0.1 to 6% of Fe, and the balance of Zn and inevitable impurities, with a Zn—Fe—Mn based alloy phase present at the interface between the iron substrate and the hot-dipped galvanizing layer, and an area ratio of the Zn—Fe—Mn-based alloy phase to the hot-dipped galvanizing layer ranging from 1 to 60%.

Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Abstract: A method for maintaining equipment by remote operation and assistance, applied in an electronic device, obtains on-site information in response to a failure notification, and queries maintenance guidance information according to the on-site information. When the maintenance guidance information exists, the electronic device displays or plays the maintenance guidance information by Augmented Reality (AR) glasses, collects user operation data of a maintenance operation in real time, compares the user operation data with the maintenance guidance information, and prompts a user to correct a maintenance operation when a comparison indicates that a current repair or maintenance operation is erroneous. When the maintenance guidance information does not exist, the electronic device establishes a connection with a remote expert terminal by the AR glasses, and obtains real-time guidance from the remote expert terminal.

Abstract: Techniques described herein include performing a first anneal operation on a first portion of the interconnect, filling the remaining portion of the interconnect, and then performing a second anneal operation on the interconnect. The two-step anneal techniques described herein enable the removal of defects in an interconnect structure, particularly for high aspect ratio interconnect structures. Accordingly, the two-step anneal techniques described herein may be used to fabricate defect free or near defect free interconnect structures in a semiconductor device. This reduces contact resistance for the interconnect structures, reduces premature device failure for the semiconductor device, increases manufacturing yield, and increases tolerance of the interconnect structures to subsequent processing operations, among other examples.

Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.