Patents by Inventor Takashi Yokoyama

Takashi Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180002203
    Abstract: A first electrode and a second electrode, and a ceramic structural body into which a gas is introduced, and which is configured to introduce into water an active species produced by a plasma which is generated between the first electrode and the second electrode are provided. The ceramic structural body and at least one electrode from among the first electrode and the second electrode are formed together in an integrated manner.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Applicant: NGK Insulators, Ltd.
    Inventors: Takashi Yokoyama, Shoji Tange, Hideki Shimizu
  • Publication number: 20180002199
    Abstract: A pulsed voltage is repeatedly applied between a first electrode and a second electrode to which a gas is supplied, a plasma is generated between the first electrode and the second electrode, and an active species is produced in the plasma. The energy necessary for plasma generation is set to a value greater than or equal to 1.8 W/cm3 and less than or equal to 8.5 W/cm3.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Applicant: NGK Insulators, Ltd.
    Inventors: Takashi YOKOYAMA, Shoji TANGE, Hideki SHIMIZU, Kazunari YAMADA
  • Patent number: 9837534
    Abstract: A semiconductor device includes: a first substrate on which a first field effect transistor is provided; and a second substrate on which a second field effect transistor of a second conductive type is provided; the first and second substrates being bonded to each other at the substrate faces thereof on which the first and second field transistors are provided, respectively; the first field effect transistor and the second field effect transistor being electrically connected to each other.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: December 5, 2017
    Assignee: Sony Corporation
    Inventor: Takashi Yokoyama
  • Patent number: 9828859
    Abstract: The gas turbine blade includes a cooling channel formed therein, and a partition disposed on its tip side for isolating the cooling channel from the outside. The partition is integrally formed with a blade portion in a position on its inner side in the radial direction with respect to the tip of the gas turbine blade. Reinforcements are provided on the outer side of the partition in the radial direction and on the inner side of the tip end wall extended from the blade portion to connect the partition with the tip end wall. Outer surface cooling holes are formed to extend from the cooling channel into communication with an outer surface of the tip end wall, and inner surface cooling holes are formed to extend from the cooling channel into an inner surface of the tip end wall through the partition.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: November 28, 2017
    Assignee: Mitsubishi Hitachi Power Systems, Ltd.
    Inventor: Takashi Yokoyama
  • Publication number: 20170277299
    Abstract: [Object] In a touch screen in which an electrode portion is formed on a base film, a pattern of the electrode portion is made less visible. [Solution] A touch screen 1 includes a first base film 11, a first transparent electrode 15, a second base film 13, a second transparent electrode 17, and a second intermediate base film 21. The first transparent electrode 15 is formed on the first base film 11. The second base film 13 is placed to face the first base film 11. The second transparent electrode 17 is formed on the second base film 13. The second intermediate base film 21 has a retardation value of 3000 nm or more and is placed so that a contraction direction thereof and contraction directions of the first base film 11 and the second base film 13 are matched.
    Type: Application
    Filed: November 18, 2015
    Publication date: September 28, 2017
    Inventors: Takashi YOKOYAMA, Takao ICHIHARA, Kenji OKUMURA, Kazuhiro NISHIKAWA
  • Publication number: 20170243920
    Abstract: A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.
    Type: Application
    Filed: May 10, 2017
    Publication date: August 24, 2017
    Inventor: Takashi Yokoyama
  • Publication number: 20170240082
    Abstract: A vehicle seat is provided with a seat cushion and a seat back. The seat back is provided with a resin frame at least a part of the rear surface side of which is exposed; a pad material disposed on the resin frame; a trim cover for covering the pad material; and a resin hook mounted to an end of the trim cover. The resin frame has a turned-back end formed by turning back outward in a U shape an end of the resin frame. The resin hook is engaged with the turned-back end. The resin hook has a protrusion at the portion thereof which is located within the turned-back end.
    Type: Application
    Filed: November 4, 2015
    Publication date: August 24, 2017
    Inventor: Takashi YOKOYAMA
  • Patent number: 9698199
    Abstract: A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: July 4, 2017
    Assignee: SONY CORPORATION
    Inventor: Takashi Yokoyama
  • Publication number: 20170141298
    Abstract: The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Taku UMEBAYASHI, Shunichi SUKEGAWA, Takashi YOKOYAMA, Masanori HOSOMI, Yutaka HIGO
  • Publication number: 20170128604
    Abstract: A treatment apparatus and a sterilization apparatus each include a liquid reservoir portion configured to store a treatment subject liquid, a plasma generation portion configured to generate a plasma on or above a liquid surface of the treatment subject liquid, and a bubble supply portion configured to generate a bubble containing the generated plasma on or above the liquid surface and configured to supply the bubble into the treatment subject liquid. Thus, the plasma is generated on or above the liquid surface of the treatment subject liquid, and the bubble containing the generated plasma is generated and supplied into the treatment subject liquid.
    Type: Application
    Filed: January 25, 2017
    Publication date: May 11, 2017
    Applicant: NGK INSULATORS, LTD.
    Inventors: Hideki SHIMIZU, Yuichiro IMANISHI, Kazunari YAMADA, Takashi YOKOYAMA
  • Publication number: 20170125475
    Abstract: A semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventor: Takashi Yokoyama
  • Patent number: 9631498
    Abstract: A gas turbine blade having a film cooling structure can reduce stress and strain that occur around the cooling holes of the film cooling structure. For example, in the gas turbine blade, a plurality of cooling holes thoroughly connected to the cooling pass formed inside the gas turbine blade are arranged in the span direction in the leading edge portion of the gas turbine blade, and the direction of the longitudinal axis of the cooling holes is made identical to the direction of principal strain occurring in the leading edge portion of the turbine blade within a range of 15 degrees.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: April 25, 2017
    Assignee: Mitsubishi Hitachi Power Systems, Ltd.
    Inventor: Takashi Yokoyama
  • Patent number: 9595562
    Abstract: A memory cell structure, a method of manufacturing a memory, and a memory apparatus that conform a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat are provided. A memory cell includes: a transistor with a first diffusion layer formed in a bottom portion of a concave portion, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first and second diffusion layers in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: March 14, 2017
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Shunichi Sukegawa, Takashi Yokoyama, Masanori Hosomi, Yutaka Higo
  • Patent number: 9577005
    Abstract: There is provided a semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: February 21, 2017
    Assignee: SONY CORPORATION
    Inventor: Takashi Yokoyama
  • Publication number: 20160322422
    Abstract: A semiconductor device of the technology includes a first diffusion section (22), a second diffusion section (21), a channel section (23), a gate section (24), and a stress application section (31, 32, or 33). In a semiconductor layer (10) having a groove (10A), the first diffusion section (22) is formed at or in the vicinity of a bottom of the groove (10A), the second diffusion section (21) is formed at an upper end of the groove (10A), and the channel section (23) is formed between the first diffusion section (22) and the second diffusion section (21). The gate section (24) is buried in the groove (10A) at a position opposing the channel section (23). The stress application section (31, 32, or 33) applies one of compressive stress and tensile stress to the channel section (23) in a normal direction to the semiconductor layer (10).
    Type: Application
    Filed: December 11, 2014
    Publication date: November 3, 2016
    Applicant: SONY CORPORATION
    Inventors: TAKASHI YOKOYAMA, TAKU UMEBAYASHI
  • Publication number: 20160293664
    Abstract: A semiconductor device including a semiconductor substrate with a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 6, 2016
    Inventors: Takashi Yokoyama, Taku Umebayashi
  • Publication number: 20160260774
    Abstract: A memory cell structure, a method of manufacturing a memory, and a memory apparatus that conform a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat are provided. A memory cell includes: a transistor with a first diffusion layer formed in a bottom portion of a concave portion, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first and second diffusion layers in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
    Type: Application
    Filed: October 10, 2014
    Publication date: September 8, 2016
    Inventors: Taku UMEBAYASHI, Shunichi SUKEGAWA, Takashi YOKOYAMA, Masanori HOSOMI, Yutaka HIGO
  • Publication number: 20160251774
    Abstract: There is provided a silicon single crystal producing method in producing a silicon single crystal by the Czochralski method using a pulling apparatus including a heat shield, wherein an oxygen concentration in the crystal is controlled through the adjustment of a flow velocity of inert gas introduced into the apparatus at the gap portion between an exterior surface of the single crystal and a lower-end opening edge of the heat shield, in accordance with a gap-to-crystal-diameter ratio (“the area of the gap portion”/“the area of a cross-sectional of the single crystal”). By this producing method, it is possible to appropriately control the oxygen concentration in the pulled single crystal.
    Type: Application
    Filed: October 31, 2014
    Publication date: September 1, 2016
    Applicant: SUMCO CORPORATION
    Inventors: Kazumi TANABE, Takashi YOKOYAMA, Tegi KIM
  • Patent number: 9412788
    Abstract: A semiconductor device includes: a semiconductor substrate including a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: August 9, 2016
    Assignee: SONY CORPORATION
    Inventors: Takashi Yokoyama, Taku Umebayashi
  • Patent number: 9407459
    Abstract: Upon receipt of an intercepted first Ethernet Frame, a communication system converts the first Ethernet Frame into a second Ethernet Frame including a second identifier based on the first identifier and the conversion information, and sends the second Ethernet Frame toward a first input/output port identified by the second identifier. The system, in sending an Ethernet Frame on which communication service has been executed from the virtual machine, converts the Ethernet Frame on which the communication service has been executed into a third Ethernet Frame including a third identifier identifying a second input/output port of the virtual machine which has executed the communication service. The system converts the third Ethernet Frame into the first Ethernet Frame including the first identifier based on the third identifier and the conversion information and sends the first Ethernet Frame toward the destination of the first Ethernet Frame.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: August 2, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Michitaka Okuno, Takashi Yokoyama, Kozo Ikegami