Patents by Inventor Takeshi Furusawa
Takeshi Furusawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8963291Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: May 20, 2011Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20150016079Abstract: A wiring board includes a first resin insulation layer, an electronic component positioned on first surface of the first insulation layer, a second resin insulation layer formed on the first surface of the first insulation layer such that the second insulation layer is embedding the electronic component, a conductive layer formed on the second insulation layer, a third resin insulation layer formed on the conductive layer and second insulation layer, and a connection via conductor formed in the second insulation layer such that the connection via conductor is connecting electrode of the electronic component and conductive layer on the second insulation layer. The first insulation layer has a pad structure on second surface side of the first insulation layer on opposite side of the first surface, and the first insulation layer has coefficient of thermal expansion set lower than coefficients of thermal expansion of the second and third insulation layers.Type: ApplicationFiled: July 11, 2014Publication date: January 15, 2015Applicant: IBIDEN CO., LTD.Inventors: Toshiki FURUTANI, Takeshi FURUSAWA, Keisuke SHIMIZU, Yuichi NAKAMURA
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Patent number: 8772648Abstract: A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.Type: GrantFiled: April 10, 2012Date of Patent: July 8, 2014Assignee: Ibiden Co., Ltd.Inventors: Toshiki Furutani, Takeshi Furusawa
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Publication number: 20140014399Abstract: A printed wiring board includes a core substrate, first and second buildup structures on surfaces of the core, respectively, and first and second solder-resist layers on the first and second structures, respectively. The core includes insulative substrate, conductive layers on surfaces of the substrate and through-hole conductor connecting the conductive layers, the first structure includes interlayer insulation layer and conductive layer in the first structure, the second structure includes interlayer insulation layer and conductive layer in the second structure, a thickness between the outer surfaces of the first and second solder-resist layers is set in range of from 150 ?m or greater and less than 380 ?m, and at least one of the core, first and second structures, and first and second solder-resist layers includes reinforcing material in amount such that the board includes the material in amount in range of from 20 to 35 vol. %.Type: ApplicationFiled: January 30, 2013Publication date: January 16, 2014Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Toshiki FURUTANI, Takeshi FURUSAWA
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Publication number: 20130241067Abstract: The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer.Type: ApplicationFiled: April 30, 2013Publication date: September 19, 2013Applicant: Renesas Electronics CorporationInventors: Takeshi FURUSAWA, Takao KAMOSHIMA, Masatsugu AMISHIRO
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Publication number: 20130221505Abstract: A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup.Type: ApplicationFiled: August 30, 2012Publication date: August 29, 2013Applicant: IBIDEN Co., Ltd.Inventors: Toshiki FURUTANI, Takeshi Furusawa
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Patent number: 8513808Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.Type: GrantFiled: April 27, 2011Date of Patent: August 20, 2013Assignee: Renesas Electronics CorporationInventors: Katsuhiko Hotta, Takeshi Furusawa, Toshikazu Matsui, Takuro Homma
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Patent number: 8487192Abstract: A printed wiring board including an insulation layer made of a resin material and having first and second surfaces, the insulation layer having an opening portion opened on the second surface, a conductive circuit having first and second surfaces, the conductive circuit being embedded in the insulation layer such that the first surface of the conductive circuit is formed flush with the first surface of the insulation layer and that the second surface of the conductive circuit is exposed through the opening portion of the insulation layer, a first surface-treatment film formed on the conductive circuit and facing the first surface of the conductive circuit, and a second surface-treatment film formed on the conductive circuit and facing the second surface of the conductive circuit and in the opening portion of the insulation layer.Type: GrantFiled: November 16, 2010Date of Patent: July 16, 2013Assignee: Ibiden Co., Ltd.Inventors: Masatoshi Kunieda, Kazuhiro Yoshikawa, Takeshi Furusawa
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Patent number: 8365402Abstract: A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.Type: GrantFiled: July 31, 2009Date of Patent: February 5, 2013Assignee: Ibiden Co., Ltd.Inventors: Toshiki Furutani, Takeshi Furusawa
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Patent number: 8347493Abstract: A method of manufacturing a wiring board with a built-in electronic component including providing a first base material having a support body and a first metal foil detachably adhered on the support body, forming a connection terminal for mounting an electronic component on the first metal foil of the first base material by an additive method, mounting an electronic component to the connection terminal such that the electronic component is electrically connected to the connection terminal and mounted on the first base material, covering the electronic component with an insulative material structure having a hollow portion such that the electronic component is accommodated in the hollow portion of the insulative material structure after the mounting and detaching the support body from the first metal foil such that a substrate having the first base material and the insulative material structure is formed.Type: GrantFiled: February 11, 2009Date of Patent: January 8, 2013Assignee: Ibiden Co., Ltd.Inventors: Hirotaka Taniguchi, Toshiki Furutani, Takeshi Furusawa, Takashi Kariya
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Publication number: 20120289032Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed. Over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11, insulating films 14, 15, 16 are formed. An opening is formed in those insulating films and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 to form the opening. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance. By interposing the insulating film 14 therebetween with a higher density of Si (silicon) atoms than the insulating film 11, an electrically weak interface is prevented from being formed.Type: ApplicationFiled: May 21, 2012Publication date: November 15, 2012Inventors: Takeshi FURUSAWA, Takao KAMOSHIMA, Masatsugu AMISHIRO, Naohito SUZUMURA, Shoichi FUKUI, Masakazu OKADA
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Publication number: 20120199389Abstract: A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.Type: ApplicationFiled: April 10, 2012Publication date: August 9, 2012Applicant: IBIDEN CO., LTD.Inventors: Toshiki FURUTANI, Takeshi Furusawa
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Patent number: 8203210Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.Type: GrantFiled: September 15, 2010Date of Patent: June 19, 2012Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Takao Kamoshima, Masatsugu Amishiro, Naohito Suzumura, Shoichi Fukui, Masakazu Okada
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Patent number: 8097948Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.Type: GrantFiled: September 13, 2010Date of Patent: January 17, 2012Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Daisuke Kodama, Masahiro Matsumoto, Hiroshi Miyazaki
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Publication number: 20110266679Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.Type: ApplicationFiled: April 27, 2011Publication date: November 3, 2011Inventors: Katsuhiko Hotta, Takeshi Furusawa, Toshikazu Matsui, Takuro Homma
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Patent number: 8018030Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: March 24, 2009Date of Patent: September 13, 2011Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20110215447Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: ApplicationFiled: May 20, 2011Publication date: September 8, 2011Applicant: Renesas Electronics CorporationInventors: Takeshi Furusawa, Norio Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20110139498Abstract: A printed wiring board including an insulation layer made of a resin material and having first and second surfaces, the insulation layer having an opening portion opened on the second surface, a conductive circuit having first and second surfaces, the conductive circuit being embedded in the insulation layer such that the first surface of the conductive circuit is formed flush with the first surface of the insulation layer and that the second surface of the conductive circuit is exposed through the opening portion of the insulation layer, a first surface-treatment film formed on the conductive circuit and facing the first surface of the conductive circuit, and a second surface-treatment film formed on the conductive circuit and facing the second surface of the conductive circuit and in the opening portion of the insulation layer.Type: ApplicationFiled: November 16, 2010Publication date: June 16, 2011Applicant: IBIDEN CO., LTD.Inventors: Masatoshi Kunieda, Kazuhiro Yoshikawa, Takeshi Furusawa
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Patent number: 7960279Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.Type: GrantFiled: June 29, 2009Date of Patent: June 14, 2011Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20110001246Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.Type: ApplicationFiled: September 15, 2010Publication date: January 6, 2011Inventors: Takeshi FURUSAWA, Takao Kamoshima, Masatsugu Amishiro, Naohito Suzumura, Shoichi Fukui, Masakazu Okada