Patents by Inventor Takeshi Furusawa

Takeshi Furusawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060006530
    Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.
    Type: Application
    Filed: July 5, 2005
    Publication date: January 12, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 6903445
    Abstract: Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: June 7, 2005
    Assignee: Renesas Technology Corp
    Inventors: Daisuke Ryuzaki, Takeshi Furusawa
  • Publication number: 20040256728
    Abstract: Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.
    Type: Application
    Filed: July 23, 2004
    Publication date: December 23, 2004
    Applicant: HITACHI, LTD.
    Inventors: Daisuke Ryuzaki, Takeshi Furusawa
  • Publication number: 20040233920
    Abstract: Each routing unit of the network routing apparatus includes: one or a plurality of transfer means each for extracting a packet header of a packet received from a line, and one or a plurality of search means each for extracting output destination information using the packet header received from each transfer means; wherein, in each routing unit, one search means is connected to one transfer means, or a plurality of transfer means are connected to one search means, or a plurality of search means are connected to one transfer means, or a plurality of search means and a plurality of transfer means are connected to one another.
    Type: Application
    Filed: February 18, 2004
    Publication date: November 25, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki Muranaka, Takeshi Furusawa, Tetsuya Nagata, Nobuhito Matsuyama, Tatsuo Kanetake
  • Patent number: 6777325
    Abstract: Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: August 17, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Daisuke Ryuzaki, Takeshi Furusawa
  • Publication number: 20040048203
    Abstract: A method of manufacturing a semiconductor device is provided. In one example, the method includes fabricating holes and/or trenches in organosiloxane insulating film without damaging the film by ashing and without causing a problem of shape deterioration or obstacles. The method comprising forming a second insulating film and a inorganic thin film soluble to a dissolving solution on an organosiloxane insulating film, fabricating the organosiloxane insulating film using the inorganic thin film as a hard mask, and removing the hard mask after fabrication by a dissolving solution.
    Type: Application
    Filed: May 29, 2003
    Publication date: March 11, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Shuntaro Machida, Daisuke Ryuzaki
  • Patent number: 6680541
    Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: January 20, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
  • Publication number: 20030201465
    Abstract: Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 30, 2003
    Inventors: Daisuke Ryuzaki, Takeshi Furusawa
  • Patent number: 6599830
    Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: July 29, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Takao Kumihashi, Shuntaro Machida
  • Patent number: 6479380
    Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: November 12, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Takao Kumihashi, Shuntaro Machida
  • Publication number: 20020164865
    Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.
    Type: Application
    Filed: July 3, 2002
    Publication date: November 7, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Takao Kumihashi, Shuntaro Machida
  • Publication number: 20020105085
    Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
    Type: Application
    Filed: January 18, 2002
    Publication date: August 8, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
  • Patent number: 6358838
    Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: March 19, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
  • Publication number: 20010046783
    Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.
    Type: Application
    Filed: May 24, 2001
    Publication date: November 29, 2001
    Inventors: Takeshi Furusawa, Takao Kumihashi, Shuntaro Machida
  • Publication number: 20010009295
    Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 26, 2001
    Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
  • Patent number: 5609511
    Abstract: Disclosed is a method of polishing a thin film layer to be polished, which is formed on the surface of a substrate, by pressing the substrate on the surface of a polishing pad and relatively moving the substrate and the polishing pad, the method comprising the steps of: detecting the position of a front surface of the thin film layer to be polished using a first sensor and also detecting the position of a bottom surface of the thin film layer using a second sensor, on the way of the polishing; calculating the residual thickness of the thin film layer on the basis of the detected positions of the front and bottom surfaces of the thin film layer; and controlling the processing condition of the subsequent polishing on the basis of the calculated residual thickness of the thin film layer.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: March 11, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Moriyama, Yoshio Kawamura, Yoshio Homma, Kikuo Kusukawa, Takeshi Furusawa
  • Patent number: 4310176
    Abstract: A seat belt locking device used with a seat belt arrangement for an automobile vehicle. The locking device locks the seat belt for protecting the driver or passenger from danger when the vehicle is suddenly decelerated in an emergency case such as a collision. The seat belt locking device of the present invention comprises a slidable but unrotatable wedge-shaped seat belt locking member having a pair of roller supporting portions between which a roller is mounted, and a pair of fixed roller shafts the cross section of which is the segment of a circle. The seat belt is so arranged as to pass around the roller of the locking member and the two roller shafts, so that the belt can be firmly caught between the two flat portions of the wedge-shaped seat belt locking member and the respective flat portions of the roller shafts, when the vehicle is suddenly decelerated.
    Type: Grant
    Filed: May 15, 1980
    Date of Patent: January 12, 1982
    Assignee: Fuji Kiko Kabushiki Kaisha
    Inventors: Takeshi Furusawa, Yoshimi Yamamoto