Patents by Inventor Takeshi Furusawa

Takeshi Furusawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100327449
    Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.
    Type: Application
    Filed: September 13, 2010
    Publication date: December 30, 2010
    Applicant: Renesas Electronics Corporation
    Inventors: Takeshi FURUSAWA, Daisuke Kodama, Masahiro Matsumoto, Hiroshi Miyazaki
  • Publication number: 20100314620
    Abstract: To suppress or prevent the generation of a crack in an insulating film below an external terminal which could be caused by an external force added to the external terminal of a semiconductor device. A top wiring layer MH of wiring layers formed on a main surface of a silicon substrate has a pad comprising a conductor pattern containing aluminum. On an undersurface of the pad, there are arranged a barrier conductor film formed by laminating, from below, a first barrier conductor film and a second barrier conductor film. Of a fifth wiring layer which is one layer lower than the top wiring layer, in an area overlapping with a probe contact area of the pad in a plane, the conductor pattern is not arranged. Further, the first and second barrier conductor films are the conductor films including titanium and titanium nitride as principal components, respectively. Also, the first barrier conductor film is thicker than the second barrier conductor film.
    Type: Application
    Filed: June 5, 2010
    Publication date: December 16, 2010
    Inventors: Takeshi FURUSAWA, Takao Kamoshima, Hiroki Takewaka
  • Patent number: 7816268
    Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: October 19, 2010
    Assignee: Renesas Elecronics Corporation
    Inventors: Takeshi Furusawa, Daisuke Kodama, Masahiro Matsumoto, Hiroshi Miyazaki
  • Publication number: 20100236822
    Abstract: A wiring board is formed with a substrate, conductive patterns laminated in the thickness direction of the substrate, multiple pads having a predetermined pitch and formed on the same layer as the conductive patterns, a conductive bonding layer arranged on each of the multiple pads, and an electronic component having electrodes. Here, the electronic component is arranged inside the substrate. The electrodes of the electronic component and the multiple pads are electrically connected to each other by means of bonding layers. Also, the height of each of the multiple pads is greater than the height of the conductive pattern adjacent to each pad. Moreover, a protective material related to the bonding layers is not formed at least on the layer where the pads and the first conductive patterns are formed.
    Type: Application
    Filed: July 7, 2009
    Publication date: September 23, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Takeshi FURUSAWA
  • Publication number: 20100151673
    Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Takeshi Furusawa, Daisuke Kodama, Masahiro Matsumoto, Hiroshi Miyazaki
  • Publication number: 20100108371
    Abstract: A wiring board with a built-in electronic component in which an electronic component is flip-chip mounted to be built in, including a conductive-pattern layer, a connection terminal formed in the conductive-pattern layer and electrically connected to the electronic component, and a solder resist layer formed on the conductive-pattern layer. The solder resist layer is formed around the connection terminal on the conductive-pattern layer, but it is not formed in at least part of the other region on the conductive-pattern layer.
    Type: Application
    Filed: June 19, 2009
    Publication date: May 6, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Takeshi FURUSAWA
  • Patent number: 7700487
    Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: April 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Furusawa, Daisuke Kodama, Masahiro Matsumoto, Hiroshi Miyazaki
  • Publication number: 20100078213
    Abstract: A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.
    Type: Application
    Filed: July 31, 2009
    Publication date: April 1, 2010
    Applicant: IBIDEN CO., LTD
    Inventors: Toshiki FURUTANI, Takeshi Furusawa
  • Publication number: 20090263963
    Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Takeshi FURUSAWA, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 7605448
    Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: October 20, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 7602063
    Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: October 13, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Publication number: 20090242255
    Abstract: A method of manufacturing a wiring board with a built-in electronic component includes providing a first base material comprising a support body and a first metal foil detachably adhered on the support body, forming a connection terminal for mounting an electronic component on the first metal foil of the first base material by an additive method, electrically connecting an electronic component and the connection terminal by arranging the electronic component on the first base material such that a surface of the electronic component on which a circuit is formed faces a surface on which the connection terminal is formed, covering the electronic component with an insulative material after the mounting, and detaching the support body and the first metal foil.
    Type: Application
    Filed: February 11, 2009
    Publication date: October 1, 2009
    Applicant: IBIDEN CO., LTD
    Inventors: Hirotaka TANIGUCHI, Toshiki Furutani, Takeshi Furusawa, Takashi Kariya
  • Publication number: 20090189245
    Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Application
    Filed: March 24, 2009
    Publication date: July 30, 2009
    Applicant: Renesas Technology Corporation
    Inventors: Takeshi FURUSAWA, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Publication number: 20090184424
    Abstract: The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 23, 2009
    Inventors: Takeshi Furusawa, Takao Kamoshima, Masatsugu Amishiro
  • Publication number: 20080230847
    Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.
    Type: Application
    Filed: January 14, 2008
    Publication date: September 25, 2008
    Inventors: Takeshi Furusawa, Takao Kamoshima, Masatsugu Amishiro, Naohito Suzumura, Shoichi Fukui, Masakazu Okada
  • Patent number: 7379456
    Abstract: Each routing unit of the network routing apparatus includes: one or a plurality of transfer means each for extracting a packet header of a packet received from a line, and one or a plurality of search means each for extracting output destination information using the packet header received from each transfer means; wherein, in each routing unit, one search means is connected to one transfer means, or a plurality of transfer means are connected to one search means, or a plurality of search means are connected to one transfer means, or a plurality of search means and a plurality of transfer means are connected to one another.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: May 27, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Muranaka, Takeshi Furusawa, Tetsuya Nagata, Nobuhito Matsuyama, Tatsuo Kanetake
  • Publication number: 20070167010
    Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.
    Type: Application
    Filed: January 12, 2007
    Publication date: July 19, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Takeshi FURUSAWA, Daisuke KODAMA, Masahiro MATSUMOTO, Hiroshi MIYAZAKI
  • Publication number: 20070114668
    Abstract: A semiconductor device is equipped with a semiconductor chip which has at least one layer of first insulating film formed on a substrate, and a plurality of pads arranged on a layer higher than the first insulating film. The plurality of pads on the semiconductor chip are arranged parallel to a predetermined chip edge of the semiconductor chip. The first insulating film has a reinforcement pattern in a region underneath each of the plurality of pads. In the region underneath each pad, occupancy of the reinforcement pattern in the first insulating film is within a predetermined range permitted for the region underneath each pad and occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction perpendicular to the predetermined chip edge is higher than occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction parallel to the chip edge.
    Type: Application
    Filed: November 20, 2006
    Publication date: May 24, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Kinya Goto, Takeshi Furusawa, Masazumi Matsuura, Noriko Miura
  • Publication number: 20060103025
    Abstract: A semiconductor device includes a low dielectric constant film having a copper interconnection formed therein, a silicon oxide film arranged above the low dielectric constant film, a surface protection film arranged above the silicon oxide film, a sealing ring formed to surround a circuit forming region, and a groove portion formed outside the sealing ring when viewed two-dimensionally. The groove portion is formed such that its bottom portion is located above the low dielectric constant film and such that the bottom portion is located below an upper end of the copper interconnection.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 18, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Takeshi Furusawa, Masahiro Matsumoto, Noboru Morimoto, Masazumi Matsuura
  • Publication number: 20060055005
    Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 16, 2006
    Applicant: Renesas Technology Corporation
    Inventors: Takeshi Furusawa, Norio Miura, Kinya Goto, Masazumi Matsuura