Patents by Inventor Takeshi Kajiyama
Takeshi Kajiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8492830Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate having a gate groove and first to third grooves, the first to third grooves being formed on a bottom surface of the gate groove and the third groove being formed between the first and second grooves, and a gate electrode having a first gate portion formed in the first groove, a second gate portion formed in the second groove, a third gate portion formed in the third groove, and a fourth gate portion formed in the gate groove. A cell transistor having the gate electrode has a first channel region formed in the semiconductor substrate between the first and third gate portions and a second channel region formed in the semiconductor substrate between the second and third gate portions.Type: GrantFiled: September 19, 2011Date of Patent: July 23, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kajiyama
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Patent number: 8357982Abstract: According to one embodiment, a magnetic memory according to an embodiment includes a magnetoresistive effect element and a fourth magnetic layer which is provided on the side surface of the magnetoresistive effect element via an insulating film. The magnetoresistive effect element has a first magnetic layer of which the magnetization direction is variable, a second magnetic layer of which the magnetization direction fixed, a third magnetic layer of which the magnetization direction parallel to a film plane is variable, and an intermediate layer between the first magnetic layer and the second magnetic layer. The fourth magnetic layer collects a magnetic field generated from the end of the third magnetic layer.Type: GrantFiled: August 31, 2010Date of Patent: January 22, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kajiyama
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Patent number: 8314464Abstract: First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion in a linear form in a channel region between the source/drain regions. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. A film thickness of the second portion of the second semiconductor layer is smaller than a film thickness of the first portion of the second semiconductor layer.Type: GrantFiled: February 4, 2010Date of Patent: November 20, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayoshi Iwayama, Yoshiaki Asao, Takeshi Kajiyama
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Patent number: 8309950Abstract: First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion on a channel region between the source/drain regions. Third semiconductor layers are on the first portions of the second semiconductor layer. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. Contact plugs are in the first semiconductor layers, the first portions of the second semiconductor layers and the third semiconductor layers in the source/drain regions. A diameter of the contact plug in the second semiconductor layer is smaller than a diameter of the contact plug in the first and third semiconductor layers.Type: GrantFiled: February 4, 2010Date of Patent: November 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayoshi Iwayama, Takeshi Kajiyama, Yoshiaki Asao
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Publication number: 20120261779Abstract: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.Type: ApplicationFiled: February 9, 2012Publication date: October 18, 2012Inventors: Takeshi KAJIYAMA, Yoshiaki ASAO
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Publication number: 20120248527Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate having a gate groove and first to third grooves, the first to third grooves being formed on a bottom surface of the gate groove and the third groove being formed between the first and second grooves, and a gate electrode having a first gate portion formed in the first groove, a second gate portion formed in the second groove, a third gate portion formed in the third groove, and a fourth gate portion formed in the gate groove. A cell transistor having the gate electrode has a first channel region formed in the semiconductor substrate between the first and third gate portions and a second channel region formed in the semiconductor substrate between the second and third gate portions.Type: ApplicationFiled: September 19, 2011Publication date: October 4, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi KAJIYAMA
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Publication number: 20120217594Abstract: According to one embodiment, a magnetic random access memory includes a semiconductor substrate, an MTJ element formed from a perpendicular magnetization film and arranged above the semiconductor substrate, and a stress film including at least one of a tensile stress film arranged on an upper side of the MTJ element to apply a stress in a tensile direction with respect to the semiconductor substrate and a compressive stress film arranged on a lower side of the MTJ element to apply a stress in a compressive direction with respect to the semiconductor substrate.Type: ApplicationFiled: September 19, 2011Publication date: August 30, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi Kajiyama
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Patent number: 8238144Abstract: A spin-transfer magnetic memory includes a magnetoresistive element having a pinned layer, a free layer and a tunnel insulating layer provided between the pinned layer and the free layer, a bit line connected to one terminal of the magnetoresistive element, a select transistor having a current path whose one terminal is connected to the other terminal of the magnetoresistive element, a source line connected to the other terminal of the current path of the select transistor, and a pulse generation circuit passing a microwave pulse current through the magnetoresistive element, and assisting a magnetization switching of the free layer in a write operation.Type: GrantFiled: March 3, 2010Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kajiyama
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Patent number: 8208289Abstract: A magnetoresistive element includes first, second, and third fixed layers, first, second, and third spacer layers, and a free layer. The first fixed layer is made of a ferromagnetic material and having an invariable magnetization direction. The first spacer layer is formed on the first fixed layer and made of an insulator. The free layer is formed on the first spacer layer, made of a ferromagnetic material, and having a variable magnetization direction. The second spacer layer is formed on the free layer and made of a nonmagnetic material. The second fixed layer is formed on the second spacer layer, made of a ferromagnetic material, and having an invariable magnetization direction. The third spacer layer is formed below the first fixed layer and made of a nonmagnetic material. The third fixed layer is formed below the third spacer layer, made of a ferromagnetic material, and having an invariable magnetization direction.Type: GrantFiled: February 11, 2009Date of Patent: June 26, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kajiyama
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Patent number: 8203193Abstract: A magnetic random access memory includes a magnetoresistive effect element which has a fixed layer, a recording layer and a non-magnetic layer provided between the fixed layer and the recording layer and in which the magnetization directions of the fixed layer and the recording layer are brought into a parallel state or an anti-parallel state in accordance with a direction of a current flowing between the fixed layer and the recording layer, a first contact which is connected to the recording layer and in which a contact area between the recording layer and the first contact is smaller than an area of the recording layer, and a cap layer which is provided between the first contact and the recording layer and which directly comes in contact with the first contact and which has a resistance higher than a resistance of the recording layer.Type: GrantFiled: June 17, 2011Date of Patent: June 19, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Kajiyama, Yoshiaki Asao, Akihiro Nitayama
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Publication number: 20120068286Abstract: According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer.Type: ApplicationFiled: September 20, 2011Publication date: March 22, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiji Hosotani, Hiroyuki Kanaya, Takeshi Kajiyama
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Patent number: 8111540Abstract: A semiconductor memory device includes first and second bit line provided in the same level layer above a semiconductor substrate, a first variable-resistance element disposed under the first bit line, having one terminal connected to one end of a current path of a first MOSFET, a second variable-resistance element disposed under the second bit line, and having one terminal connected to one end of a current path of a second MOSFET, a first interconnect layer connecting the first bit line to the other terminal of the first variable-resistance element, and connecting the first bit line to the other end of the current path of the second MOSFET, and a second interconnect layer connecting the second bit line to the other terminal of the second variable-resistance element, and connecting the second bit line to the other end of the current path of the first MOSFET.Type: GrantFiled: September 14, 2009Date of Patent: February 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Asao, Takeshi Kajiyama, Tsuneo Inaba
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Publication number: 20120008367Abstract: According to one embodiment, a resistance change type memory includes a memory cell and a capacitor which are provided on a semiconductor substrate. The memory cell includes a resistance change type memory and a select transistor. The resistance change type storage element changes in resistance value in accordance with data to be stored. The select transistor includes a first semiconductor region provided in the semiconductor substrate, and a gate electrode facing the side surface of the first semiconductor region via a gate insulating film. The capacitor includes a second semiconductor region provided in the semiconductor substrate, a capacitor electrode facing the side surface of the second semiconductor region, and a first capacitor insulating film provided between the second semiconductor region and the capacitor electrode.Type: ApplicationFiled: September 21, 2010Publication date: January 12, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi KAJIYAMA
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Patent number: 8081505Abstract: A magnetoresistive element includes a stacked structure including a fixed layer having a fixed direction of magnetization, a recording layer having a variable direction of magnetization, and a nonmagnetic layer sandwiched between the fixed layer and the recording layer, a first protective film covering a circumferential surface of the stacked structure, and made of silicon nitride, and a second protective film covering a circumferential surface of the first protective film, and made of silicon nitride. A hydrogen content in the first protective film is not more than 4 at %, and a hydrogen content in the second protective film is not less than 6 at %.Type: GrantFiled: September 9, 2009Date of Patent: December 20, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Kajiyama, Yoshiaki Asao, Shigeki Takahashi, Minoru Amano, Kuniaki Sugiura
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Publication number: 20110283299Abstract: A disk laminate includes thin disks laminated to each other, which are to be suctioned and conveyed; and spacers provided between the thin disks to prevent the thin disks from directly contacting each other, the spacers having air permeability.Type: ApplicationFiled: May 12, 2011Publication date: November 17, 2011Inventors: Yoshimichi Takano, Nobuaki Onagi, Kohji Tsukahara, Haruki Tokumaru, Daiichi Koide, Takeshi Kajiyama, Masami Nishida
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Patent number: 8058080Abstract: A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resist by setting a first template or a second template into contact with the resist and curing the resist. The first template has the first pattern that corresponds to the magnetoresistive element and the lower electrode. The second template has the second pattern that corresponds to the magnetoresistive element and the upper electrode. The magnetic material and the lower electrode are patterned at the same time by using the resist having the first pattern, or the magnetic material and the upper electrode are patterned at the same time by using the resist having the second pattern.Type: GrantFiled: February 3, 2010Date of Patent: November 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Kajiyama, Yoshiaki Asao, Minoru Amano, Shigeki Takahashi, Masayoshi Iwayama, Kuniaki Sugiura
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Publication number: 20110254112Abstract: A semiconductor memory device includes a semiconductor substrate, and plural switching transistors provided on the semiconductor substrate. A contact plug is embedded between the adjacent two switching transistors described above, is insulated from gates of the adjacent two switching transistors, and is electrically connected to diffusion layers of the adjacent two switching transistors. An upper connector is formed on the contact plug, and an upper surface is at a position higher than upper surfaces of the switching transistors. A memory element is provided on the upper surface of the upper connector, and stores data. A wiring is provided on the memory element.Type: ApplicationFiled: January 27, 2011Publication date: October 20, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takaya YAMANAKA, Yoshiaki ASAO, Takeshi KAJIYAMA, Minoru AMANO, Masayoshi IWAYAMA, Kuniaki SUGIURA, Yukinori KOYAMA
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Publication number: 20110248365Abstract: A magnetic random access memory includes a magnetoresistive effect element which has a fixed layer, a recording layer and a non-magnetic layer provided between the fixed layer and the recording layer and in which the magnetization directions of the fixed layer and the recording layer are brought into a parallel state or an anti-parallel state in accordance with a direction of a current flowing between the fixed layer and the recording layer, a first contact which is connected to the recording layer and in which a contact area between the recording layer and the first contact is smaller than an area of the recording layer, and a cap layer which is provided between the first contact and the recording layer and which directly comes in contact with the first contact and which has a resistance higher than a resistance of the recording layer.Type: ApplicationFiled: June 17, 2011Publication date: October 13, 2011Inventors: Takeshi KAJIYAMA, Yoshiaki Asao, Akihiro Nitayama
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Publication number: 20110233661Abstract: According to one embodiment, a semiconductor memory device includes a fin-shaped active area, a gate electrode, a silicide layer, and a contact. The fin-shaped active area is provided in a semiconductor substrate and has a first side, a second side parallel to the first side, and a top face connecting the first and second sides. The gate electrode is formed in a trench formed in the active area such that it crosses the trench and is a part of a word line insulated from the active area. The silicide layer is located in the active area on either side of the gate electrode and is formed at least on the first side of the active area serving as a source and a drain region. The contact is connected to the silicide layer and connects at least a storage element.Type: ApplicationFiled: March 18, 2011Publication date: September 29, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi Kajiyama
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Publication number: 20110233697Abstract: According to one embodiment, a magnetic memory according to an embodiment includes a magnetoresistive effect element and a fourth magnetic layer which is provided on the side surface of the magnetoresistive effect element via an insulating film. The magnetoresistive effect element has a first magnetic layer of which the magnetization direction is variable, a second magnetic layer of which the magnetization direction fixed, a third magnetic layer of which the magnetization direction parallel to a film plane is variable, and an intermediate layer between the first magnetic layer and the second magnetic layer. The fourth magnetic layer collects a magnetic field generated from the end of the third magnetic layer.Type: ApplicationFiled: August 31, 2010Publication date: September 29, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi KAJIYAMA