Patents by Inventor Takeshi Kajiyama

Takeshi Kajiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080165454
    Abstract: A magnetic random access memory includes a magnetoresistive effect element which includes a fixed layer in which a magnetization direction is fixed, a recording layer in which a magnetization direction is reversible, and a nonmagnetic layer formed between the fixed layer and the recording layer, and in which the magnetization directions in the fixed layer and the recording layer take one of a parallel state and an antiparallel state in accordance with a direction of an electric current supplied between the fixed layer and the recording layer, and a yoke layer which concentrates a magnetic field generated by the electric current, and causes the magnetic field to act on magnetization in the recording layer.
    Type: Application
    Filed: December 19, 2007
    Publication date: July 10, 2008
    Inventor: Takeshi KAJIYAMA
  • Publication number: 20080135958
    Abstract: A magnetic random access memory includes a magnetoresistive effect element which has a fixed layer, a recording layer and a non-magnetic layer provided between the fixed layer and the recording layer and in which the magnetization directions of the fixed layer and the recording layer are brought into a parallel state or an anti-parallel state in accordance with a direction of a current flowing between the fixed layer and the recording layer, a first contact which is connected to the recording layer and in which a contact area between the recording layer and the first contact is smaller than an area of the recording layer, and a cap layer which is provided between the first contact and the recording layer and which directly comes in contact with the first contact and which has a resistance higher than a resistance of the recording layer.
    Type: Application
    Filed: November 20, 2007
    Publication date: June 12, 2008
    Inventors: Takeshi KAJIYAMA, Yoshiaki Asao, Akihiro Nitayama
  • Publication number: 20080089118
    Abstract: A magnetic random access memory includes a magnetoresistive effect element having a fixed layer in which a magnetization direction is fixed, a recording layer in which a magnetization direction is reversible, and a nonmagnetic layer formed between the fixed layer and the recording layer, a hollow portion being formed in a center of the recording layer, and the magnetization directions in the fixed layer and the recording layer taking one of a parallel state and an antiparallel state in accordance with a direction of an electric current supplied between the fixed layer and the recording layer, an insulating layer formed in the hollow portion, a wiring connected to one terminal of the magnetoresistive effect element, and a transistor connected to the other terminal of the magnetoresistive effect element.
    Type: Application
    Filed: May 4, 2007
    Publication date: April 17, 2008
    Inventor: Takeshi Kajiyama
  • Patent number: 7277318
    Abstract: A write wiring for writing information in an MTJ device is covered with a magnetic layer. The magnetic layer has a structure in which the growing direction of columnar grains is 30° or less from the normal-line direction of sidewalls, a structure in which grains are deposited of sidewalls, a structure in which grains are deposited like a layer, or a structure in which grains are amorphously deposited.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: October 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yoda, Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Takeshi Kajiyama, Yoshiaki Asao
  • Patent number: 7262449
    Abstract: A magnetic random access memory according to an aspect of the present invention comprises a first magnetic layer in which a magnetization state is fixed, a second magnetic layer which has a shape different from that of the first magnetic layer and in which a magnetization state varies in accordance with write data, a non-magnetic layer which is arranged between the first magnetic layer and the second magnetic layer, and a third magnetic layer which surrounds the second magnetic layer.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: August 28, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Publication number: 20070164265
    Abstract: A semiconductor memory device includes a first write line which is provided in a first direction, a first memory element which is connected to the first write line, a second memory element which is provided to neighbor the first memory element in the first direction, and is connected to the first write line, a first insulation film which is provided on surfaces of the first and second memory elements, and a second insulation film which is provided between the neighboring first and second memory elements and has a lower heat conductivity than the first insulation film.
    Type: Application
    Filed: November 27, 2006
    Publication date: July 19, 2007
    Inventor: Takeshi Kajiyama
  • Patent number: 7205564
    Abstract: A resistance change memory includes a memory element, and a first organic semiconductor layer in contact with the memory element.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: April 17, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 7200034
    Abstract: A magnetic memory device includes a magnetoresistance effect element, and a first write interconnection which is arranged under the magnetoresistance effect element and has a first interconnection layer and a first yoke layer, the first interconnection layer having a portion projecting toward the magnetoresistance effect element, and the first yoke layer including a first, a second, and third regions. And the device includes a second write interconnection which is arranged above the magnetoresistance effect element and has a second interconnection layer and a second yoke layer, the second interconnection layer having a portion projecting toward the magnetoresistance effect element, and the second yoke layer including a fourth, a fifth, and sixth regions.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: April 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kajiyama, Tomomasa Ueda, Tatsuya Kishi, Hiroaki Yoda, Hisanori Aikawa, Masatoshi Yoshikawa
  • Patent number: 7151691
    Abstract: MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. A first conductive line functioning as a read line and extending in the X direction is connected to pin layers of the MTJ elements. A second conductive line functioning as a write line and read line and extending in the X direction is connected to free layers of the MTJ elements. A write line extends in the Y direction and is shared with two MTJ elements present above and below the write line. The two MTJ elements present above and below the write line are arranged symmetric to the write line.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: December 19, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 7148550
    Abstract: A semiconductor device includes a memory portion in which a plurality of magneto-resistance effect elements each having a hard-axis of magnetization and an easy-axis of magnetization are arranged and one of binary data is written in all the magneto-resistance effect elements, and a circuit portion to which a write current is supplied to write only the other one of the binary data in only a selected magneto-resistance effect element selected from the magneto-resistance effect elements.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: December 12, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 7141842
    Abstract: A magnetic memory device includes a memory cell which has a first wiring line composed of a first wiring layer, a second wiring line composed of a second wiring layer and provided above or below the first wiring line so as to cross the first wiring line, and a magnetoresistive effect element device provided in a position where the first wiring line and the second wiring line cross each other. The device further includes a peripheral circuit which includes a third wiring line provided around the memory cell and composed of the first wiring layer, a fourth wiring line provided above or below the third wiring line and composed of the second wiring layer, and at least one magnetic layer forming the magnetoresistive effect element device and provided between the third wiring line and the fourth wiring line.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: November 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Publication number: 20060262595
    Abstract: MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. A first conductive line functioning as a read line and extending in the X direction is connected to pin layers of the MTJ elements. A second conductive line functioning as a write line and read line and extending in the X direction is connected to free layers of the MTJ elements. A write line extends in the Y direction and is shared with two MTJ elements present above and below the write line. The two MTJ elements present above and below the write line are arranged symmetric to the write line.
    Type: Application
    Filed: July 10, 2006
    Publication date: November 23, 2006
    Inventor: Takeshi Kajiyama
  • Patent number: 7135735
    Abstract: A semiconductor device comprising: a support substrate; an embedded insulating layer formed on the support substrate; a semiconductor layer on the embedded insulating layer; at least an element region formed in the semiconductor layer; a plurality of source/drain regions of a first conductivity type, formed in the element region at predetermined intervals; a plurality of body regions of a second conductivity type, sandwiched between a pair of adjacent ones of the source/drain regions in the element region; and a gate formed on each of the body regions with a gate insulating film being laid between them, each of the source/drain regions including: an inner high-concentration portion extending to the embedded insulating layer, and an outer low-concentration portion surrounding the inner high-concentration portion and having a direct contact with the body regions.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: November 14, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Takeshi Kajiyama
  • Publication number: 20060132984
    Abstract: A magnetic memory device includes a magnetoresistance effect element, and a first write interconnection which is arranged under the magnetoresistance effect element and has a first interconnection layer and a first yoke layer, the first interconnection layer having a portion projecting toward the magnetoresistance effect element, and the first yoke layer including a first, a second, and third regions. And the device includes a second write interconnection which is arranged above the magnetoresistance effect element and has a second interconnection layer and a second yoke layer, the second interconnection layer having a portion projecting toward the magnetoresistance effect element, and the second yoke layer including a fourth, a fifth, and sixth regions.
    Type: Application
    Filed: February 18, 2005
    Publication date: June 22, 2006
    Inventors: Takeshi Kajiyama, Tomomasa Ueda, Tatsuya Kishi, Hiroaki Yoda, Hisanori Aikawa, Masatoshi Yoshikawa
  • Patent number: 7064402
    Abstract: A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: June 20, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kajiyama, Tomomasa Ueda, Tatsuya Kishi, Hisanori Aikawa, Masatoshi Yoshikawa, Yoshiaki Asao, Hiroaki Yoda
  • Patent number: 7061032
    Abstract: A semiconductor device including: a cell transistor including: a pair of source and drain regions formed in a surface portion of a silicon substrate so as to have a predetermined space therebetween; a channel region sandwiched by the source and drain regions; a gate formed above the channel region with a gate dielectric film being formed therebetween; and a silicon plug formed on the silicon substrate, the silicon plug electrically contacting the source and drain regions, an upper portion of the silicon plug being a first self-aligned silicide portion.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 7061036
    Abstract: Magnetic random access memory including a cell array stacked in a plurality of plane levels, a plurality of write wirings disposed on each of the stacked cell array, and a contact plug commonly or independently coupled to the plurality of stacked array planes. Also, a method for manufacturing magnetic random access memory so as to reduce influences of parasitic wiring resistances due to differences of the writing current values for supplying the stacked cell array. The magnetic random access memory includes a cell array of TMR elements stacked in a plurality of plane levels, a plurality of write wirings being formed so that a parasitic resistance becomes smaller accompanying a longer distance from a drive current source, and one or a plurality of contact plugs for commonly or independently coupling to the plurality of stacked array planes.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 6984865
    Abstract: A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: January 10, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kajiyama, Tomomasa Ueda, Tatsuya Kishi, Hisanori Aikawa, Masatoshi Yoshikawa, Yoshiaki Asao, Hiroaki Yoda
  • Publication number: 20050281079
    Abstract: A write wiring for writing information in an MTJ device is covered with a magnetic layer. The magnetic layer has a structure in which the growing direction of columnar grains is 300 or less from the normal-line direction of sidewalls, a structure in which grains are deposited like a layer, or a structure in which grains are amorphously deposited.
    Type: Application
    Filed: August 30, 2005
    Publication date: December 22, 2005
    Inventors: Hiroaki Yoda, Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20050275000
    Abstract: A magnetic memory device includes a first write wiring line including a wiring layer formed in a trench in an insulation layer, a barrier metal layer buried in the trench over the wiring layer. And the device includes a magneto-resistance effect element provided on the first write wiring line.
    Type: Application
    Filed: August 13, 2004
    Publication date: December 15, 2005
    Inventors: Takeshi Kajiyama, Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Masatoshi Yoshikawa