Patents by Inventor Takeshi Kajiyama

Takeshi Kajiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7741688
    Abstract: A magnetic random access memory includes a magnetoresistive effect element having a fixed layer in which a magnetization direction is fixed, a recording layer in which a magnetization direction is reversible, and a nonmagnetic layer formed between the fixed layer and the recording layer, a hollow portion being formed in a center of the recording layer, and the magnetization directions in the fixed layer and the recording layer taking one of a parallel state and an antiparallel state in accordance with a direction of an electric current supplied between the fixed layer and the recording layer, an insulating layer formed in the hollow portion, a wiring connected to one terminal of the magnetoresistive effect element, and a transistor connected to the other terminal of the magnetoresistive effect element.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: June 22, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 7727778
    Abstract: A magnetoresistive element includes a stack formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed, a first nonmagnetic layer, a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, a first circumferential wall provided on the second nonmagnetic layer in contact with a circumferential surface of the second fixed layer to surround the second fixed layer, and made of an insulator, and a second circumferential wall provided on the first nonmagnetic layer in contact with a circumferential surface of the free layer to surround the free layer, and made of an insulator.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayoshi Iwayama, Keiji Hosotani, Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20100103718
    Abstract: A semiconductor memory device includes first and second bit line provided in the same level layer above a semiconductor substrate, a first variable-resistance element disposed under the first bit line, having one terminal connected to one end of a current path of a first MOSFET, a second variable-resistance element disposed under the second bit line, and having one terminal connected to one end of a current path of a second MOSFET, a first interconnect layer connecting the first bit line to the other terminal of the first variable-resistance element, and connecting the first bit line to the other end of the current path of the second MOSFET, and a second interconnect layer connecting the second bit line to the other terminal of the second variable-resistance element, and connecting the second bit line to the other end of the current path of the first MOSFET.
    Type: Application
    Filed: September 14, 2009
    Publication date: April 29, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki ASAO, Takeshi KAJIYAMA, Tsuneo INABA
  • Publication number: 20100102407
    Abstract: A magnetoresistive element includes a stacked structure including a fixed layer having a fixed direction of magnetization, a recording layer having a variable direction of magnetization, and a nonmagnetic layer sandwiched between the fixed layer and the recording layer, a first protective film covering a circumferential surface of the stacked structure, and made of silicon nitride, and a second protective film covering a circumferential surface of the first protective film, and made of silicon nitride. A hydrogen content in the first protective film is not more than 4 at %, and a hydrogen content in the second protective film is not less than 6 at %.
    Type: Application
    Filed: September 9, 2009
    Publication date: April 29, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Kajiyama, Yoshiaki Asao, Shigeki Takahashi, Minoru Amano, Kuniaki Sugiura
  • Publication number: 20100097846
    Abstract: A magnetic memory includes an interlayer insulation layer provided on a substrate, a conductive underlying layer provided on the interlayer insulation layer, and a magnetoresistive element provided on the underlying layer and including two magnetic layers and a nonmagnetic layer interposed between the magnetic layers. The underlying layer has an etching rate lower than an etching rate of each of the magnetic layers.
    Type: Application
    Filed: September 21, 2009
    Publication date: April 22, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kuniaki Sugiura, Takeshi Kajiyama, Yoshiaki Asao, Shigeki Takahashi, Minoru Amano
  • Publication number: 20100053823
    Abstract: A magnetoresistive element includes a stack formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed, a first nonmagnetic layer, a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, a first circumferential wall provided on the second nonmagnetic layer in contact with a circumferential surface of the second fixed layer to surround the second fixed layer, and made of an insulator, and a second circumferential wall provided on the first nonmagnetic layer in contact with a circumferential surface of the free layer to surround the free layer, and made of an insulator.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 4, 2010
    Inventors: Masayoshi Iwayama, Keiji Hosotani, Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20100002492
    Abstract: A resistance change type memory includes a first device region and first and second bit lines provided above the first device region and along a first direction. First and second resistance change elements are connected to the first and second bit lines, respectively. A first transistor is serially connected to both the first and second resistance change elements, formed in the first device region, and has a first gate electrode extending along a second direction which intersects with the first direction. The first gate electrode has a gate width equal to a width in the second direction of the first device region.
    Type: Application
    Filed: July 3, 2009
    Publication date: January 7, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takeshi KAJIYAMA
  • Patent number: 7629637
    Abstract: A magnetic random access memory includes first and second bit lines extending in a first direction, the second bit line being adjacent to the first bit line in a second direction, a first magnetoresistive effect element being connected to the first bit line and having a first fixed layer, a first recording layer, and a first nonmagnetic layer, and a second magnetoresistive effect element being adjacent to the first magnetoresistive effect element in the second direction and being connected to the second bit line and having a second fixed layer, a second recording layer, and a second nonmagnetic layer, the first and second recording layers being formed by a same first layer extending in the second direction.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: December 8, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kajiyama, Tsuneo Inaba
  • Patent number: 7598577
    Abstract: A magnetic memory device comprises magneto-resistance elements each including a cylindrical fixed magnetization layer, an insulating film which covers an external surface of the fixed magnetization layer, and a free magnetization layer which faces the fixed magnetization layer through the insulating film and covers a surface of the insulating film, wherein a magnetization direction of the fixed magnetization layer is parallel to a central axis direction of the cylinder.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: October 6, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Publication number: 20090206426
    Abstract: A magnetoresistive element includes first, second, and third fixed layers, first, second, and third spacer layers, and a free layer. The first fixed layer is made of a ferromagnetic material and having an invariable magnetization direction. The first spacer layer is formed on the first fixed layer and made of an insulator. The free layer is formed on the first spacer layer, made of a ferromagnetic material, and having a variable magnetization direction. The second spacer layer is formed on the free layer and made of a nonmagnetic material. The second fixed layer is formed on the second spacer layer, made of a ferromagnetic material, and having an invariable magnetization direction. The third spacer layer is formed below the first fixed layer and made of a nonmagnetic material. The third fixed layer is formed below the third spacer layer, made of a ferromagnetic material, and having an invariable magnetization direction.
    Type: Application
    Filed: February 11, 2009
    Publication date: August 20, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takeshi KAJIYAMA
  • Patent number: 7564109
    Abstract: A magnetic memory device includes a first write wiring line including a wiring layer formed in a trench in an insulation layer, a barrier metal layer buried in the trench over the wiring layer. And the device includes a magneto-resistance effect element provided on the first write wiring line.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: July 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kajiyama, Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Masatoshi Yoshikawa
  • Publication number: 20090154224
    Abstract: A spin transfer type magnetic random access memory includes a magnetoresistive effect element including a fixed layer, a recording layer, and a nonmagnetic layer, a source line connected to one terminal of the magnetoresistive effect element, a transistor having a current path whose one end is connected to the other terminal of the magnetoresistive effect element, a bit line connected to the other end of the current path of the transistor, and running parallel to the source line, and a source/sinker which supplies a write current between the source line and the bit line via the magnetoresistive effect element and the transistor, a direction in which a magnetic field generated by the write current having passed through the bit line is applied to the magnetoresistive effect element being opposite to a direction of the write current passing through the magnetoresistive effect element.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 18, 2009
    Inventor: Takeshi Kajiyama
  • Publication number: 20080308887
    Abstract: A semiconductor memory device includes first to third wiring layers formed above a semiconductor substrate, extending in a first direction, and sequentially arranged in a second direction perpendicular to the first direction, a plurality of active areas formed in the semiconductor substrate, and extending in a direction oblique to the first direction, first and second selection transistors formed in each of the active areas, and sharing a source region electrically connected to the second wiring layer, a first magnetoresistive element having one terminal electrically connected to a drain region of the first selection transistor, and the other terminal electrically connected to the first wiring layer, and a second magnetoresistive element having one terminal electrically connected to a drain region of the second selection transistor, and the other terminal electrically connected to the third wiring layer.
    Type: Application
    Filed: November 21, 2007
    Publication date: December 18, 2008
    Inventors: Yoshiaki Asao, Takeshi Kajiyama
  • Publication number: 20080265347
    Abstract: A magnetoresistive element includes a first stacked structure formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed and a first nonmagnetic layer, a second stacked structure formed on the first stacked structure by sequentially stacking a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, and a circumferential wall formed in contact with a circumferential surface of the second stacked structure to surround the second stacked structure, and made of an insulator. A circumferential surface of the first stacked structure is substantially perpendicular. The second stacked structure has a tapered shape which narrows upward.
    Type: Application
    Filed: April 23, 2008
    Publication date: October 30, 2008
    Inventors: Masayoshi Iwayama, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani
  • Publication number: 20080204944
    Abstract: It is possible to reduce writing current without causing fluctuation of the writing characteristic. A magnetic memory includes: a magnetoresistance effect element having a magnetization pinned layer whose magnetization direction is pinned, a storage layer whose magnetization direction is changeable, and a non-magnetic layer provided between the magnetization pinned layer and the storage layer; and a first wiring layer which is electrically connected to the magnetoresistance effect element and extends in a direction substantially perpendicular to a direction of an easy magnetization axis of the storage layer, an end face of the magnetoresistance effect element substantially perpendicular to the direction of the easy magnetization axis of the storage layer and an end face of the first wiring layer substantially perpendicular to the direction of the easy magnetization axis being positioned on the same plane.
    Type: Application
    Filed: April 10, 2008
    Publication date: August 28, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Takeshi Kajiyama, Yoshiaki Asao, Hiroaki Yoda
  • Publication number: 20080205126
    Abstract: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 28, 2008
    Inventors: Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20080205125
    Abstract: A magnetic random access memory includes first and second bit lines extending in a first direction, the second bit line being adjacent to the first bit line in a second direction, a first magnetoresistive effect element being connected to the first bit line and having a first fixed layer, a first recording layer, and a first nonmagnetic layer, and a second magnetoresistive effect element being adjacent to the first magnetoresistive effect element in the second direction and being connected to the second bit line and having a second fixed layer, a second recording layer, and a second nonmagnetic layer, the first and second recording layers being formed by a same first layer extending in the second direction.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 28, 2008
    Inventors: Takeshi KAJIYAMA, Tsuneo Inaba
  • Publication number: 20080209118
    Abstract: A magnetic random access memory includes a semiconductor substrate in which a step portion having a side surface and a top face is formed, a gate electrode formed on the side surface of the step portion through a gate insulating film, a drain diffusion layer formed in the top face of the step portion, a source diffusion layer formed in the semiconductor substrate below the drain diffusion layer to be separated from the drain diffusion layer, a magnetoresistive effect element which is connected with the drain diffusion layer, and has a fixed layer, a recording layer and a non-magnetic layer, the magnetization directions of the fixed layer and the recording layer entering a parallel state or an antiparallel state in accordance with a direction of a current flowing through a space between the fixed layer and the recording layer, and a bit line connected with the magnetoresistive effect element.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 28, 2008
    Inventor: Takeshi KAJIYAMA
  • Publication number: 20080185670
    Abstract: A magnetic random access memory includes an interlayer dielectric film having a contact hole, a contact formed in the contact hole, a first barrier metal film formed on an upper surface of the contact and buried in the contact hole, a magnetoresistive effect element having one terminal connected to the first barrier metal film, and including a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, the magnetization directions in the fixed layer and the recording layer taking one of a parallel state and an antiparallel state in accordance with a direction of an electric current flowing between the fixed layer and the recording layer, a wiring connected to the other terminal of the magnetoresistive effect element, and a transistor connected to the magnetoresistive effect element via the contact and the first barrier metal film.
    Type: Application
    Filed: October 10, 2007
    Publication date: August 7, 2008
    Inventor: Takeshi KAJIYAMA
  • Patent number: 7405962
    Abstract: MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. A first conductive line functioning as a read line and extending in the X direction is connected to pin layers of the MTJ elements. A second conductive line functioning as a write line and read line and extending in the X direction is connected to free layers of the MTJ elements. A write line extends in the Y direction and is shared with two MTJ elements present above and below the write line. The two MTJ elements present above and below the write line are arranged symmetric to the write line.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama