Patents by Inventor Takeshi Shioga
Takeshi Shioga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110073993Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: FUJITSU LIMITEDInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Publication number: 20110056068Abstract: The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.Type: ApplicationFiled: November 12, 2010Publication date: March 10, 2011Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
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Patent number: 7867869Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.Type: GrantFiled: June 11, 2003Date of Patent: January 11, 2011Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7863524Abstract: The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.Type: GrantFiled: September 20, 2007Date of Patent: January 4, 2011Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
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Publication number: 20100321911Abstract: A capacitor including a substrate; a conductive layer provided on the substrate and containing conductive particles; a valve metal sheet having a dielectric part formed throughout an entire surface of the conductive layer; a protection layer covering the valve metal sheet; a first electrode terminal electrically connected to the conductive layer and partially exposed from an external surface of the protection layer; and a second electrode terminal electrically connected to a surface of the valve metal sheet which is opposite to a surface of the valve metal sheet on which the dielectric part is provided, and the second electrode terminal partially exposed from the external surface of the protection layer; wherein the dielectric part is made of an oxide of a metallic material of the valve metal sheet, the dielectric part is formed with a corrugated surface on the conductive layer, and the conductive particles of the conductive layer are in contact with the corrugated surface of the dielectric part.Type: ApplicationFiled: August 4, 2010Publication date: December 23, 2010Applicant: FUJITSU LIMITEDInventors: Takeshi SHIOGA, Kazuaki KURIHARA
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Patent number: 7846852Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).Type: GrantFiled: May 19, 2010Date of Patent: December 7, 2010Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Masataka Mizukoshi, Kazuaki Kurihara
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Patent number: 7832069Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed on a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).Type: GrantFiled: April 27, 2007Date of Patent: November 16, 2010Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Publication number: 20100264951Abstract: Recesses are formed on one surface of a substrate. A conductive film covers an inner surface of each of the recesses. This conductive film contacts a bump of a semiconductor device to be inspected and is electrically connected to the bump. It is therefore possible to prevent damages of the bump to be caused by contact of a probe pin.Type: ApplicationFiled: June 28, 2010Publication date: October 21, 2010Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Kazuaki Kurihara
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Publication number: 20100233359Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).Type: ApplicationFiled: May 19, 2010Publication date: September 16, 2010Applicant: FUJITSU LIMITEDInventors: Takeshi SHIOGA, Masataka MIZUKOSHI, Kazuaki KURIHARA
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Patent number: 7793396Abstract: A manufacturing method includes forming a dielectric part by oxidizing an entire first surface of a valve metal sheet; forming a through hole in the valve metal sheet in which the dielectric part is formed; applying an adhesive conductive material to a surface of a substrate; attaching the valve metal sheet in which the through hole is formed, to the substrate so that the first surface contacts the conductive material on the substrate surface; forming a conductive layer by curing the conductive material; forming a protection layer which covers a second surface of the valve metal sheet which is opposite to the first surface of the valve metal sheet; forming openings in the protection layer, so that the conductive layer in the through hole and the second surface of the valve metal sheet are partially exposed from the openings; and filling up the openings in the protection layer with another conductive material to form electrode terminals.Type: GrantFiled: September 19, 2007Date of Patent: September 14, 2010Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7795739Abstract: A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate so as to be electrically connected to the through vias; and multiple external connection terminals provided on a second main surface of the Si substrate so as to be electrically connected to the through vias. The second main surface faces away from the first main surface. The semiconductor chip is provided on one of the first main surface and the second main surface so as to be electrically connected to the through vias. The Si substrate has a thickness less than the diameter of the through holes.Type: GrantFiled: November 16, 2007Date of Patent: September 14, 2010Assignee: Fujitsu LimitedInventors: Kazuaki Kurihara, Takeshi Shioga, John D. Baniecki
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Patent number: 7778009Abstract: A thin-film capacitor element having two conductive films and a dielectric film sandwiched therebetween is provided above a substrate. An inorganic protective film covering the thin-film capacitor element and having a second opening exposing at least a part of the conductive films is provided. An organic protective film covering the thin-film capacitor element from above the inorganic protective film and having a first opening therein, which is larger than the second opening and exposes the second opening, is provided. Besides, a bump connected with the conductive films via the first opening and the second opening is provided.Type: GrantFiled: January 29, 2007Date of Patent: August 17, 2010Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Masatoshi Ishii, Kazuaki Kurihara, Teru Nakanishi, Masataka Mizukoshi
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Patent number: 7745924Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).Type: GrantFiled: May 30, 2008Date of Patent: June 29, 2010Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Masataka Mizukoshi, Kazuaki Kurihara
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Patent number: 7726198Abstract: A strain sensor comprises a capacitor formed on a substrate, the capacitor having a layered structure in which a lower electrode, a metal oxide film of perovskite structure and an upper electrode are laminated consecutively on the substrate, the capacitor being adapted to be mounted upon a specimen, and a measuring circuit that measures a leakage current flowing through the capacitor between the upper electrode and the lower electrode.Type: GrantFiled: September 10, 2007Date of Patent: June 1, 2010Assignee: Fujitsu LimitedInventors: John D. Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Publication number: 20100112775Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.Type: ApplicationFiled: January 8, 2010Publication date: May 6, 2010Applicant: FUJITSU LIMITEDInventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
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Patent number: 7670940Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.Type: GrantFiled: October 17, 2005Date of Patent: March 2, 2010Assignee: Fujitsu LimitedInventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
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Patent number: 7618859Abstract: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the growth direction of the dielectric film while the concentration of the Ba cation is non-uniform along the growth direction such that a reduced Ba-I region in which the average concentration of perovskite type Ba cations (Ba-I) is less than the average concentration of non-perovskite type Ba cations (Ba-II) exists at or near the boundary between at least one of the top and bottom electrodes, with ratio R=(atm % Ba-I)/[(atm % Ba-I)+(atm % Ba-II)] within a range of 0.1<R<0.2.Type: GrantFiled: July 24, 2008Date of Patent: November 17, 2009Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7614142Abstract: A method for fabricating an interposer includes: forming on one primary surface of a first substrate a thin-film capacitor including a first capacitor electrode, a crystalline capacitor dielectric film formed on the first electrode and a second capacitor electrode formed on the dielectric film; and forming on the primary surface of the first substrate and the capacitor a first layer as semi-cured, and a first partial electrode to be a part of a through-electrode, buried in the first resin layer and electrically connected to the first electrode or the second electrode.Type: GrantFiled: February 5, 2008Date of Patent: November 10, 2009Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
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Patent number: 7557014Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.Type: GrantFiled: November 16, 2006Date of Patent: July 7, 2009Assignee: Fujitsu LimitedInventors: Keishiro Okamoto, Takeshi Shioga, Osamu Taniguchi, Koji Omote, Yoshihiko Imanaka, Yasuo Yamagishi
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Publication number: 20090057827Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).Type: ApplicationFiled: May 30, 2008Publication date: March 5, 2009Applicant: FUJITSU LIMITEDInventors: Takeshi SHIOGA, Masataka MIZUKOSHI, Kazuaki KURIHARA