Patents by Inventor Takeshi Shioga

Takeshi Shioga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090059545
    Abstract: A semiconductor device includes a semiconductor element, a supporting substrate where the semiconductor element is mounted, and a capacitor provided on the semiconductor element and coupled to the supporting substrate via an outside connection terminal. The capacitor includes a valve metal part, an anodic oxide film formed on a surface of the valve metal part, and a conductive part formed on the anodic oxide film and made of a conductive material.
    Type: Application
    Filed: May 2, 2008
    Publication date: March 5, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi SHIOGA, Kazuaki KURIHARA
  • Patent number: 7491996
    Abstract: A capacitive element includes a base member 10, an underlying insulating film 11 formed on the base member 10, a capacitor Q constructed by forming a lower electrode 13, a capacitor dielectric film 14, and an upper electrode 15 sequentially on the underlying insulating film 11, a lower protection insulating film 16a formed on the upper electrode 15 to cover at least a part of the capacitor Q, and an upper protection insulating film 16b formed on the lower protection insulating film 16a and having a wider energy band gap than the lower protection insulating film 16a.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: February 17, 2009
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Publication number: 20090007405
    Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed on a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).
    Type: Application
    Filed: April 27, 2007
    Publication date: January 8, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Publication number: 20080315358
    Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).
    Type: Application
    Filed: August 15, 2008
    Publication date: December 25, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Patent number: 7466152
    Abstract: A probe card including probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: December 16, 2008
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Publication number: 20080305607
    Abstract: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the growth direction of the dielectric film while the concentration of the Ba cation is non-uniform along the growth direction such that a reduced Ba-I region in which the average concentration of perovskite type Ba cations (Ba-I) is less than the average concentration of non-perovskite type Ba cations (Ba-II) exists at or near the boundary between at least one of the top and bottom electrodes, with ratio R=(atm % Ba-I)/[(atm % Ba-I)+(atm % Ba-II)] within a range of 0.1<R<0.2.
    Type: Application
    Filed: July 24, 2008
    Publication date: December 11, 2008
    Applicant: FUJITSU LIMITED
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 7456078
    Abstract: The thin-film capacitor comprises a capacitor part 20 formed over a base substrate 10 and including a first capacitor electrode 14, a capacitor dielectric film 16 formed over the first capacitor electrode 14, and a second capacitor electrode 18 formed over the capacitor dielectric film 16; leading-out electrodes 26a, 26b lead from the first capacitor electrode 14 or the second capacitor electrode 18 and formed of a conducting barrier film which prevents the diffusion of hydrogen or water; and outside connection electrodes 34a, 34b for connecting to outside and connected to the leading-out electrodes 26a, 26b.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 25, 2008
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki, Masatoshi Ishii
  • Publication number: 20080257487
    Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.
    Type: Application
    Filed: June 18, 2008
    Publication date: October 23, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
  • Patent number: 7439199
    Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: October 21, 2008
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Patent number: 7417276
    Abstract: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the growth direction of the dielectric film while the concentration of the Ba cation is non-uniform along the growth direction such that a reduced Ba-I region in which the average concentration of perovskite type Ba cations (Ba-I) is less than the average concentration of non-perovskite type Ba cations (Ba-II) exists at or near the boundary between at least one of the top and bottom electrodes, with ratio R=(atm % Ba-I)/[(atm % Ba-I)+(atm % Ba-II)] within a range of 0.1<R<0.2.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 7405921
    Abstract: In one aspect of the invention, a thin layer capacitor element has a capacitor with a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, and a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: July 29, 2008
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki, Mamoru Kurashina
  • Patent number: 7405366
    Abstract: An interposer 2 including a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further including: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: July 29, 2008
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
  • Publication number: 20080134499
    Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.
    Type: Application
    Filed: February 5, 2008
    Publication date: June 12, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
  • Publication number: 20080099888
    Abstract: A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate so as to be electrically connected to the through vias; and multiple external connection terminals provided on a second main surface of the Si substrate so as to be electrically connected to the through vias. The second main surface faces away from the first main surface. The semiconductor chip is provided on one of the first main surface and the second main surface so as to be electrically connected to the through vias. The Si substrate has a thickness less than the diameter of the through holes.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 1, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Kazuaki Kurihara, Takeshi Shioga, John Baniecki
  • Patent number: 7365327
    Abstract: An SiO2 layer (3), a Ti layer (4), a Pt layer (5), a PLZT layer (6) and an IrO2 layer (7) are formed sequentially on an Si substrate (2). The IrO2 layer (7) functioning as a top electrode has a thickness of about 100 nm. Since the IrO2 layer (7) has conductivity lower than that of Pt or the like conventionally used as a top electrode and a skin depth deeper than that of Pt or the like, sufficient sensitivity can be attained by a thickness of about 100 nm.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: April 29, 2008
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 7355290
    Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: April 8, 2008
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
  • Publication number: 20080073110
    Abstract: The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.
    Type: Application
    Filed: September 20, 2007
    Publication date: March 27, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
  • Publication number: 20080072684
    Abstract: A strain sensor comprises a capacitor formed on a substrate, the capacitor having a layered structure in which a lower electrode, a metal oxide film of perovskite structure and an upper electrode are laminated consecutively on the substrate, the capacitor being adapted to be mounted upon a specimen, and a measuring circuit that measures a leakage current flowing through the capacitor between the upper electrode and the lower electrode.
    Type: Application
    Filed: September 10, 2007
    Publication date: March 27, 2008
    Applicant: FUJITSU LIMITED
    Inventors: John D. BANIECKI, Takeshi SHIOGA, Kazuaki KURIHARA
  • Patent number: 7349195
    Abstract: The present invention provides the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: March 25, 2008
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurhara
  • Publication number: 20080068780
    Abstract: A capacitor comprises a substrate, a conductive layer containing conductive particles, a valve metal sheet having a dielectric part formed throughout an entire surface of the conductive layer, a protection layer covering the valve metal sheet. The capacitor further includes a first electrode terminal electrically connected to the conductive layer and partially exposed from a surface of the protection layer, and a second electrode terminal electrically connected to a surface of the valve metal sheet opposite to a surface of the valve metal sheet on which the dielectric part is provided, and the second electrode terminal partially exposed from the surface of the protection layer. The dielectric part is made of an oxide of a metallic material of the valve metal sheet, the dielectric part is formed with a corrugated surface on the conductive layer, and the conductive particles are in contact with the corrugated surface.
    Type: Application
    Filed: September 19, 2007
    Publication date: March 20, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi SHIOGA, Kazuaki KURIHARA