Patents by Inventor Takeshi Shioga
Takeshi Shioga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7339277Abstract: A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducing film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducing film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance.Type: GrantFiled: February 16, 2005Date of Patent: March 4, 2008Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Kazuaki Karasawa, Kazuaki Kurihara
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Patent number: 7326989Abstract: A thin film capacitor is provided which includes a single crystal high dielectric constant dielectric layer. The thin film capacitor has a single crystal silicon substrate, a single crystal intermediate layer epitaxially grown on the single crystal silicon substrate, a single crystal lower electrode epitaxially grown on the single crystal intermediate layer, a single crystal high dielectric constant dielectric layer epitaxially grown on the lower electrode layer, an upper electrode layer formed above the single crystal high dielectric constant dielectric layer, and a plurality of conductor terminals connected to the lower electrode layer and upper electrode layer at a plurality of positions.Type: GrantFiled: February 28, 2005Date of Patent: February 5, 2008Assignee: FUJITSU LimitedInventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki
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Patent number: 7298050Abstract: A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate so as to be electrically connected to the through vias; and multiple external connection terminals provided on a second main surface of the Si substrate so as to be electrically connected to the through vias. The second main surface faces away from the first main surface. The semiconductor chip is provided on one of the first main surface and the second main surface so as to be electrically connected to the through vias. The Si substrate has a thickness less than the diameter of the through holes.Type: GrantFiled: October 26, 2005Date of Patent: November 20, 2007Assignee: Fujitsu LimitedInventors: Kazuaki Kurihara, Takeshi Shioga, John D. Baniecki
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Publication number: 20070232017Abstract: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the growth direction of the dielectric film while the concentration of the Ba cation is non-uniform along the growth direction such that a reduced Ba-I region in which the average concentration of perovskite type Ba cations (Ba-I) is less than the average concentration of non-perovskite type Ba cations (Ba-II) exists at or near the boundary between at least one of the top and bottom electrodes, with ratio R=(atm % Ba-I)/[(atm % Ba-I)+(atm % Ba-II)] within a range of 0.1<R<0.2.Type: ApplicationFiled: October 18, 2006Publication date: October 4, 2007Applicant: FUJITSU LIMITEDInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Publication number: 20070205486Abstract: A thin film capacitor device of the present invention has a thin film capacitor having two electrodes and a dielectric layer provided therebetween and external terminals electrically connected to the electrodes. In addition, the thin film capacitor device also has resistor layers which are provided between the external terminals and the electrodes and adjacent thereto, and which are formed of a material have a higher resistivity than that of the adjacent electrodes.Type: ApplicationFiled: September 13, 2006Publication date: September 6, 2007Applicant: FUJITSU LIMITEDInventors: Takeshi SHIOGA, Kazuaki Kurihara
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Publication number: 20070176175Abstract: A thin-film capacitor element having two conductive films and a dielectric film sandwiched therebetween is provided above a substrate. An inorganic protective film covering the thin-film capacitor element and having a second opening exposing at least a part of the conductive films is provided. An organic protective film covering the thin-film capacitor element from above the inorganic protective film and having a first opening therein, which is larger than the second opening and exposes the second opening, is provided. Besides, a bump connected with the conductive films via the first opening and the second opening is provided.Type: ApplicationFiled: January 29, 2007Publication date: August 2, 2007Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Masatoshi Ishii, Kazuaki Kurihara, Teru Nakanishi, Masataka Mizukoshi
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Patent number: 7251117Abstract: A semiconductor device having the thin film capacitor includes a first electrode formed on a substrate, a capacitor insulating film containing a laminated film, which is constructed by laminating an amorphous dielectric film and a polycrystalline dielectric film via a wave-like interface, on the first electrode, and a second electrode formed on the capacitor insulating film.Type: GrantFiled: September 15, 2004Date of Patent: July 31, 2007Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Publication number: 20070141800Abstract: The thin-film capacitor comprises a capacitor part 20 formed over a base substrate 10 and including a first capacitor electrode 14, a capacitor dielectric film 16 formed over the first capacitor electrode 14, and a second capacitor electrode 18 formed over the capacitor dielectric film 16; leading-out electrodes 26a, 26b lead from the first capacitor electrode 14 or the second capacitor electrode 18 and formed of a conducting barrier film which prevents the diffusion of hydrogen or water; and outside connection electrodes 34a, 34b for connecting to outside and connected to the leading-out electrodes 26a, 26b.Type: ApplicationFiled: March 31, 2006Publication date: June 21, 2007Applicant: FUJITSU LIMITEDInventors: Kazuaki Kurihara, Takeshi Shioga, John Baniecki, Masatoshi Ishii
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Patent number: 7227736Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed an a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).Type: GrantFiled: February 15, 2005Date of Patent: June 5, 2007Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Publication number: 20070090546Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.Type: ApplicationFiled: January 25, 2006Publication date: April 26, 2007Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John Baniecki, Kazuaki Kurihara
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Publication number: 20070076348Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.Type: ApplicationFiled: January 26, 2006Publication date: April 5, 2007Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Yoshikatsu Ishizuki, John Baniecki, Kazuaki Kurihara
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Publication number: 20070065981Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.Type: ApplicationFiled: November 16, 2006Publication date: March 22, 2007Applicant: FUJITSU LIMITEDInventors: Keishiro Okamoto, Takeshi Shioga, Osamu Taniguchi, Koji Omote, Yoshihiko Imanaka, Yasuo Yamagishi
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Patent number: 7180119Abstract: The capacitor according to the present invention comprises a lower electrode 18 formed on a base substrate 14, a dielectric film 20 formed on the lower electrode 18, and an upper electrode 28 formed on the dielectric film 20 and including a polycrystalline conduction film 22, and a amorphous conduction film 24 formed on the polycrystalline conduction film 22. Because of the amorphous conduction film 24 included in the upper electrode 28, which can shut off hydrogen and water, hydrogen and water can be prohibited from arriving at the dielectric film 20. Accordingly, the dielectric film 20 of an oxide is prevented from being reduced with hydrogen, and the capacitor can have good electric characteristics.Type: GrantFiled: May 21, 2004Date of Patent: February 20, 2007Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Publication number: 20070034989Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).Type: ApplicationFiled: October 17, 2006Publication date: February 15, 2007Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, John Baniecki, Kazuaki Kurihara
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Patent number: 7176556Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.Type: GrantFiled: March 8, 2002Date of Patent: February 13, 2007Assignee: Fujitsu LimitedInventors: Keishiro Okamoto, Takeshi Shioga, Osamu Taniguchi, Koji Omote, Yoshihiko Imanaka, Yasuo Yamagishi
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Publication number: 20070031590Abstract: The present invention comprises the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.Type: ApplicationFiled: October 16, 2006Publication date: February 8, 2007Applicant: FUJITSU LIMITEDInventors: John Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7172945Abstract: A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode layer and an upper electrode layer, and conductor members respectively connected to the lower electrode layer and the upper electrode layer, wherein at least the dielectric layer has a side face having a sufficient slope for preventing the short circuit of the upper electrode layer with the lower electrode layer through the conductor member. A method of manufacturing such a thin film capacitor is also disclosed.Type: GrantFiled: October 28, 2004Date of Patent: February 6, 2007Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Patent number: 7161200Abstract: A capacitive element which includes: a silicon substrate (base material) 1; a base insulating film 2 formed on the silicon substrate 1; and a capacitor Q constituted by forming a bottom electrode 4a, a capacitor dielectric film 5a and a top electrode 6a on the base insulating film 2. The capacitive element is characterized in that the capacitor dielectric film 5a is composed of a material with the formula (Ba1?y,Sry)mYpTiQO3+?, where 0<p/(p+m+Q)?0.015, ?0.5<?<0.5.Type: GrantFiled: December 20, 2004Date of Patent: January 9, 2007Assignee: Fujitsu LimitedInventors: John David Baniecki, Kenji Nomura, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7161793Abstract: In one aspect of the invention, in a thin layer capacitor element comprising a capacitor having a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.Type: GrantFiled: November 13, 2003Date of Patent: January 9, 2007Assignee: Fujitsu LimitedInventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki, Mamoru Kurashina
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Publication number: 20060255816Abstract: A probe card including probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.Type: ApplicationFiled: July 14, 2006Publication date: November 16, 2006Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, John Baniecki, Kazuaki Kurihara