Patents by Inventor Tatsuya Naito
Tatsuya Naito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11043582Abstract: Provided is a semiconductor device comprising: a semiconductor substrate; a gate trench section that is provided from an upper surface to an inside of the semiconductor substrate and extends in a predetermined extending direction on the upper surface of the semiconductor substrate; a mesa section in contact to the gate trench section in an arrangement direction orthogonal the extending direction; and an interlayer dielectric film provided above the semiconductor substrate; wherein the interlayer dielectric film is provided above at least a part of the gate trench section in the arrangement direction; a contact hole through which the mesa section is exposed is provided to the interlayer dielectric film; and a width of the contact hole in the arrangement direction is equal to or greater than a width of the mesa section in the arrangement direction.Type: GrantFiled: November 27, 2019Date of Patent: June 22, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Publication number: 20210175231Abstract: A semiconductor device that allows easy hole extraction is provided. The semiconductor device includes: a semiconductor substrate having drift and base regions; a transistor portion formed in the semiconductor substrate; and a diode portion formed adjacent to the transistor portion and in the semiconductor substrate. In the transistor portion and the diode portion: a plurality of trench portions each arrayed along a predetermined array direction; and a plurality of mesa portions formed between respective trench portions are formed, among the plurality of mesa portions, at least one boundary mesa portion at a boundary between the transistor portion and the diode portion includes a contact region at an upper surface of the semiconductor substrate and having a concentration higher than that of the base region, and an area of the contact region at the boundary mesa portion is greater than an area of the contact region at another mesa portion.Type: ApplicationFiled: February 10, 2021Publication date: June 10, 2021Inventor: Tatsuya NAITO
-
Patent number: 11031471Abstract: A semiconductor device is provided, including: a first conductivity-type drift region formed in the semiconductor substrate; a second conductivity-type base region formed between the upper surface of the semiconductor substrate and the drift region; a first conductivity-type accumulation region formed between the drift region and the base region and having a higher doping concentration than the drift region; and a dummy trench portion formed to penetrate the base region from the upper surface of the semiconductor substrate, wherein at least one of the accumulation region and the dummy trench portion has a suppressing structure that suppresses formation of a second conductivity-type inversion layer in a first conductivity-type region adjacent to the dummy trench portion.Type: GrantFiled: April 13, 2020Date of Patent: June 8, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10991801Abstract: A semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction.Type: GrantFiled: January 26, 2020Date of Patent: April 27, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10985158Abstract: To improve the withstand capability of a transistor portion, provided is a semiconductor device including a semiconductor substrate; a transistor portion provided in the semiconductor substrate; and a diode portion provided in the semiconductor substrate and arranged adjacent to the transistor portion in a predetermined arrangement direction. The transistor portion includes a collector region provided in a bottom surface of the semiconductor substrate, at respective ends adjacent to the diode portion; and a first low injection region that is provided on a bottom surface side of the semiconductor substrate farther inward than the respective ends, and has a carrier injection density from the bottom surface side to a top surface side of the semiconductor substrate that is lower than that of the collector region.Type: GrantFiled: March 4, 2019Date of Patent: April 20, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10957758Abstract: To improve the turn-off withstand capability of a semiconductor device. A semiconductor device is provided, including: a semiconductor substrate; an active portion that is provided in the semiconductor substrate and through which current flows between upper and lower surfaces of the semiconductor substrate; a transistor portion provided in the active portion; a diode portion provided in the active portion, and arrayed next to the transistor portion along a predetermined array direction in a top view of the semiconductor substrate; and an edge termination structure portion provided between a peripheral end of the semiconductor substrate and the active portion in the top view. In the top view, at at least part of the edge termination structure portion, which part facing the transistor portion in the direction of extension orthogonal to the array direction, a first-conductivity type first cathode region is provided in contact with the lower surface.Type: GrantFiled: March 7, 2019Date of Patent: March 23, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10957690Abstract: The reverse recovery withstand capability of a semiconductor device is improved. A semiconductor device is provided, including: a semiconductor substrate; an active portion that is provided in the substrate and through which current flows between upper and lower surfaces of the substrate; a transistor portion provided in the active portion; a diode portion provided in the active portion and arrayed next to the transistor portion along a predetermined array direction in a top view of the substrate; and an edge termination structure portion provided between a peripheral end of the substrate and the active portion in the top view. The lifetime control region including a lifetime killer is provided on an upper-surface side of the substrate and in a range from the diode portion to at least part of the edge termination structure portion, facing the diode portion in a direction of extension orthogonal to the array direction.Type: GrantFiled: March 7, 2019Date of Patent: March 23, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Publication number: 20210074836Abstract: There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.Type: ApplicationFiled: November 18, 2020Publication date: March 11, 2021Inventor: Tatsuya NAITO
-
Publication number: 20210074813Abstract: A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a gate trench portion extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the gate trench portion in an array direction orthogonal to the extending direction; a first-conductivity-type accumulation region provided above the drift region and in contact with the gate trench portion, and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region and in contact with the gate trench portion; and a second-conductivity-type floating region provided below the accumulation region and in contact with the gate trench portion, and provided in a part of the mesa portion in the array direction.Type: ApplicationFiled: November 18, 2020Publication date: March 11, 2021Inventor: Tatsuya NAITO
-
Patent number: 10930647Abstract: A semiconductor device that allows easy hole extraction is provided. The semiconductor device includes: a semiconductor substrate having drift and base regions; a transistor portion formed in the semiconductor substrate; and a diode portion formed adjacent to the transistor portion and in the semiconductor substrate. In the transistor portion and the diode portion: a plurality of trench portions each arrayed along a predetermined array direction; and a plurality of mesa portions formed between respective trench portions are formed, among the plurality of mesa portions, at least one boundary mesa portion at a boundary between the transistor portion and the diode portion includes a contact region at an upper surface of the semiconductor substrate and having a concentration higher than that of the base region, and an area of the contact region at the boundary mesa portion is greater than an area of the contact region at another mesa portion.Type: GrantFiled: February 21, 2018Date of Patent: February 23, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Publication number: 20210050435Abstract: A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.Type: ApplicationFiled: November 1, 2020Publication date: February 18, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya NAITO
-
Publication number: 20200373418Abstract: There is provided a semiconductor device comprising: a semiconductor substrate; an emitter region of a first conductivity type provided inside the semiconductor substrate; a base region of a second conductivity type provided below the emitter region inside the semiconductor substrate; an accumulation region of the first conductivity type provided below the base region inside the semiconductor substrate, and containing hydrogen as an impurity; and a trench portion provided to pass through the emitter region, the base region and the accumulation region from an upper surface of the semiconductor substrate.Type: ApplicationFiled: August 10, 2020Publication date: November 26, 2020Inventor: Tatsuya NAITO
-
Patent number: 10847617Abstract: A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a gate trench portion extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the gate trench portion in an array direction orthogonal to the extending direction; a first-conductivity-type accumulation region provided above the drift region and in contact with the gate trench portion, and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region and in contact with the gate trench portion; and a second-conductivity-type floating region provided below the accumulation region and in contact with the gate trench portion, and provided in a part of the mesa portion in the array direction.Type: GrantFiled: December 3, 2018Date of Patent: November 24, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10847613Abstract: A semiconductor device is provided. The semiconductor device includes a mesa portion provided inside the semiconductor substrate and in contact with the gate trench portion, wherein the mesa portion has, at an end portion of an upper surface thereof, a shoulder portion in contact with the gate trench portion, the shoulder portion has an outwardly convex shape, the mesa portion has a first conductivity type emitter region that: is in contact with the gate trench portion and positioned between the upper surface of the semiconductor substrate and the drift region; and has a doping concentration higher than the drift region, a lower end of the emitter region at a position in contact with the gate trench portion is located at a deeper position in the depth direction than a lower end of the emitter region at a middle, in the transverse direction, of the mesa portion.Type: GrantFiled: December 21, 2018Date of Patent: November 24, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10847640Abstract: There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.Type: GrantFiled: July 25, 2018Date of Patent: November 24, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10840361Abstract: There is provided a semiconductor device comprising: a semiconductor substrate; an emitter region of a first conductivity type provided inside the semiconductor substrate; a base region of a second conductivity type provided below the emitter region inside the semiconductor substrate; an accumulation region of the first conductivity type provided below the base region inside the semiconductor substrate, and containing hydrogen as an impurity; and a trench portion provided to pass through the emitter region, the base region and the accumulation region from an upper surface of the semiconductor substrate.Type: GrantFiled: July 26, 2018Date of Patent: November 17, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10840363Abstract: A semiconductor device having a semiconductor substrate is provided, the semiconductor substrate including: two trench sections extending in a predetermined direction; a mesa section provided between the two trench sections; and a drift layer, the mesa section including: an emitter region; a contact region; and multiple accumulation layers provided side by side in a depth direction below the emitter region and the contact region, and at least one accumulation layer among the multiple accumulation layers provided below at least a part of the emitter region, but not provided below a partial region of the contact region.Type: GrantFiled: November 28, 2018Date of Patent: November 17, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10833182Abstract: A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.Type: GrantFiled: October 23, 2018Date of Patent: November 10, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10825923Abstract: A semiconductor device is provided comprising a semiconductor substrate of a first conductivity type and a dummy trench portion having a main body portion and one or more branch portions, the main body portion formed in a front surface of the semiconductor substrate and extending in a predetermined extending direction, the branch portions extending from the main body portion in directions different from the extending direction. The semiconductor substrate has an emitter region of first conductivity type and a base region of a second conductivity type which are provided sequentially from the front surface side of the semiconductor substrate, and the dummy trench portion has a dummy trench which penetrates the emitter region and the base region from the front surface of the semiconductor substrate, and a dummy insulating portion which is provided within the dummy trench.Type: GrantFiled: June 24, 2019Date of Patent: November 3, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
-
Patent number: 10818782Abstract: At a portion at which a gate trench is branched, the trench is formed at a deeper position than at portions of the gate trench having a linear shape. A semiconductor device is provided, including: a first conductivity-type semiconductor substrate; a second conductivity-type base region provided at a front surface side of the semiconductor substrate; a first trench portion provided extending from a front surface of the semiconductor substrate and penetrating the base region; and a second conductivity-type contact region which is provided in a part of the base region at a front surface side of the semiconductor substrate and has a higher impurity concentration than the base region, wherein the first trench portion has a branch portion on the front surface of the semiconductor substrate, and the branch portion is provided being surrounded by the contact region on the front surface of the semiconductor substrate.Type: GrantFiled: November 29, 2017Date of Patent: October 27, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito