Abstract: A semiconductor device includes a semiconductor substrate including a drift region of a first conductivity type, a transistor portion provided in the substrate, and an adjacent element portion provided in the substrate, the adjacent element and transistor portions being arranged along an arrangement direction. The transistor and adjacent element portions both include a base region of a second conductivity type provided above the drift region, trench portions formed through the base region, extending in an extending direction orthogonal to the arrangement direction on the upper surface, and having a conducting portion therein, and a first lower surface side lifetime control region provided, on a lower surface side, continuously from the transistor portion to the adjacent element portion and includes a lifetime killer. The lifetime control region is provided over entirety of the transistor portion and in a part of the adjacent element portion in a top view of the substrate.

Abstract: To provide a semiconductor apparatus including: a semiconductor substrate having a drift region; an emitter region provided inside the semiconductor substrate and above the drift region; a base region provided between the emitter and drift regions; an accumulation region provided between the base and drift regions; and a plurality of gate trench portions provided to penetrate the accumulation region from an upper surface of the semiconductor substrate. The base region has: a low concentration base region provided in contact with the gate trench portions; and a high concentration base region provided apart from the gate trench portions and having a doping concentration higher than the low concentration base region. The high concentration base region is provided below the emitter region, and a width of the high concentration base region in a depth direction of the semiconductor substrate is larger than 0.1 ?m.

Abstract: A semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction.

Abstract: A semiconductor device is provided, including: a semiconductor substrate; an active section in which current flows between upper and lower surfaces of the semiconductor substrate; a transistor section provided in the active section; a gate metal layer to supply a gate voltage to the transistor section; a gate pad electrically connected to the gate metal layer; a temperature-sensing unit provided above the active section; a temperature-measurement pad arranged in a peripheral region between the active section and an outermost perimeter of the semiconductor substrate; and a temperature-sensing wire having a longitudinal portion and connecting the temperature-sensing unit and the temperature-measurement pad, wherein on the upper surface of the semiconductor substrate, the gate pad is arranged in a region other than an extending region that is an extension of the longitudinal portion of the temperature-sensing wire to the outermost perimeter of the semiconductor substrate in the longitudinal direction.

Abstract: A semiconductor device including: a semiconductor substrate; a first gate trench portion and a dummy trench portion provided from an upper surface of the semiconductor substrate to a drift region, extending in the extending direction; a first transistor mesa portion sandwiched by the first gate trench portion and dummy trench portion; a base region contacting with the first gate trench portion above the drift region; an emitter region contacting with the same on the semiconductor substrate upper surface; and a second conductivity type region exposed on the semiconductor substrate upper surface, wherein the emitter region and second conductivity type region are arranged alternately in the extending direction; and the emitter region width in the extending direction contacting with the first gate trench portion is greater than the second conductivity type region width in the extending direction contacting with the same, will be provided.

Abstract: Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode.

Abstract: When formed to have a lattice pattern, trenches are deeper at the portions thereof corresponding to the vertices of the lattice pattern than at the portions thereof corresponding to the sides. Such variations in the depths of trenches may disadvantageously result in variations in the gate threshold voltages (Vth). A semiconductor device includes two first trenches extending in a first direction with a predetermined region being sandwiched therebetween, where the predetermined region is provided in a semiconductor substrate on a front surface side thereof, and a second trench provided in the predetermined region, the second trench being spatially spaced away from the first trenches and being shorter than any of the first trenches. Here, the first and second trenches each include a trench insulating film, and a trench electrode in contact with the trench insulating film.

Abstract: An ultrasonic probe includes: a piezoelectric element that transmits and receives an ultrasonic wave; one or a plurality of acoustic matching layers disposed on a subject side of the piezoelectric element; and a conductor layer that applies a voltage to the piezoelectric element, wherein the conductor layer is disposed between the piezoelectric element and the acoustic matching layer, or between the plurality of acoustic matching layers, a magnitude of an acoustic impedance of the conductor layer is between a magnitude of an acoustic impedance of a layer disposed on one surface side of the conductor layer and a magnitude of an acoustic impedance of a layer disposed on the other surface side of the conductor layer, and the conductor layer has a Vickers hardness (Hv) of 50 or more and 600 or less.

Abstract: A super junction MOSFET device including a semiconductor substrate; a base region provided on a primary surface side of the semiconductor substrate and having impurities of a first conductivity type; a source region that includes a portion of a frontmost surface of the base region and has impurities of a second conductivity type; a gate electrode that penetrates through the base region; a source electrode that is provided on the base region and is electrically connected to the source region; and a front surface region that is provided on an entirety of the frontmost surface of the base region in a region differing from a region where the source region and the gate electrode are provided in the base region, is electrically connected to the source electrode provided on the base region, and has a lower impurity concentration of impurities of the second conductivity type than the source region.

Abstract: A semiconductor device including: a drift region formed on a semiconductor substrate; a gate trench portion provided on an upper surface of the semiconductor substrate; a first and second mesa portion adjacent to one and the other of the gate trench portions; an accumulation region provided above the drift region in the first mesa portion; a base region provided above the accumulation region; a emitter region provided between the base region and the upper surface of the semiconductor substrate; an intermediate region provided above the drift region in the second mesa portion; a contact region provided above the intermediate region, wherein the gate trench portion has a gate conductive portion; a bottom portion of the gate conductive portion has a first step and second step; and, at least part of the intermediate region is provided between the steps and the bottom portion of the gate trench portion will be provided.

Abstract: A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof.

Abstract: A semiconductor device including: drift regions formed on a semiconductor substrate; gate trench portions extending in predetermined extending directions from a semiconductor substrate upper surface; first and second mesa portions being in direct contact with one and the other sides of a gate trench portion side wall respectively; accumulation regions being in direct contact with the gate trench portions, above the drift regions, and having doping concentration higher than drift region concentration; a base region being in direct contact with the gate trench portions, above the accumulation regions; emitter regions being in direct contact with the one side wall of a gate trench portion on a semiconductor substrate upper surface in the first mesa portion, and having doping concentration higher than drift region concentration; and electrically floating second conductivity type floating regions provided spaced from the gate trench portion below the base region in the second mesa portion is provided.

Abstract: To provide a semiconductor device, wherein each of a transistor portion and a diode portion that are arrayed along an array direction has: a second-conductivity type base region provided above a first-conductivity type drift region inside a semiconductor substrate; a plurality of trench portions that penetrate the base region from an upper surface of the semiconductor substrate, extend at the upper surface of the semiconductor substrate and in a direction of extension perpendicular to the array direction, and have conductive portions provided therein; and a lower-surface side lifetime control region that lies on a lower-surface side in the semiconductor substrate, and from the transistor portion to the diode portion, and includes a lifetime killer. In the array direction, the transistor portion may have a portion provided with the lower-surface side lifetime control region, and another portion not provided with the lower-surface side lifetime control region.

Abstract: An ultrasound diagnostic apparatus includes a transmitter which transmits, to an ultrasound probe including a plurality of transducers which are arranged in a plurality of regions in a short axis direction and arranged in a long axis direction in each of the regions and can transmit and receive ultrasound independently in the plurality of regions in the short axis direction, a driving signal in each of the regions, a receiver which receives a receiving signal in each of the regions from the ultrasound probe, and a hardware processor which generates ultrasound image data from the received receiving signal in the region, extracts an image of a puncture needle inserted into a subject from the generated ultrasound image data in the region, and calculates a shift angle of the puncture needle to the ultrasound probe using boundary position information of the extracted image of the puncture needle in the region.

Abstract: A semiconductor device is provided comprising a semiconductor substrate of a first conductivity type and a dummy trench portion having a main body portion and one or more branch portions, the main body portion formed in a front surface of the semiconductor substrate and extending in a predetermined extending direction, the branch portions extending from the main body portion in directions different from the extending direction. The semiconductor substrate has an emitter region of first conductivity type and a base region of a second conductivity type which are provided sequentially from the front surface side of the semiconductor substrate, and the dummy trench portion has a dummy trench which penetrates the emitter region and the base region from the front surface of the semiconductor substrate, and a dummy insulating portion which is provided within the dummy trench.

Abstract: The reverse recovery withstand capability of a semiconductor device is improved. A semiconductor device is provided, including: a semiconductor substrate; an active portion that is provided in the substrate and through which current flows between upper and lower surfaces of the substrate; a transistor portion provided in the active portion; a diode portion provided in the active portion and arrayed next to the transistor portion along a predetermined array direction in a top view of the substrate; and an edge termination structure portion provided between a peripheral end of the substrate and the active portion in the top view. The lifetime control region including a lifetime killer is provided on an upper-surface side of the substrate and in a range from the diode portion to at least part of the edge termination structure portion, facing the diode portion in a direction of extension orthogonal to the array direction.

Abstract: The present invention provides a semiconductor device comprising (a) a semiconductor substrate, (b) a gate trench portion provided from an upper surface of the semiconductor substrate into the semiconductor substrate and extends on an upper surface of the semiconductor substrate in a predetermined extending direction, (c) a gate insulating film provided on an inner wall of the gate trench portion, (d) an interlayer dielectric film provided above the semiconductor substrate; and (e) a protective insulating film, which is, in contact with the gate insulating film, provided between the interlayer dielectric film and the gate trench portion in the depth direction of the semiconductor substrate, and is made of a different material from the interlayer dielectric film and the gate insulating film.

Abstract: To improve the turn-off withstand capability of a semiconductor device. A semiconductor device is provided, including: a semiconductor substrate; an active portion that is provided in the semiconductor substrate and through which current flows between upper and lower surfaces of the semiconductor substrate; a transistor portion provided in the active portion; a diode portion provided in the active portion, and arrayed next to the transistor portion along a predetermined array direction in a top view of the semiconductor substrate; and an edge termination structure portion provided between a peripheral end of the semiconductor substrate and the active portion in the top view. In the top view, at at least part of the edge termination structure portion, which part facing the transistor portion in the direction of extension orthogonal to the array direction, a first-conductivity type first cathode region is provided in contact with the lower surface.

Abstract: To improve the withstand capability of a transistor portion, provided is a semiconductor device including a semiconductor substrate; a transistor portion provided in the semiconductor substrate; and a diode portion provided in the semiconductor substrate and arranged adjacent to the transistor portion in a predetermined arrangement direction. The transistor portion includes a collector region provided in a bottom surface of the semiconductor substrate, at respective ends adjacent to the diode portion; and a first low injection region that is provided on a bottom surface side of the semiconductor substrate farther inward than the respective ends, and has a carrier injection density from the bottom surface side to a top surface side of the semiconductor substrate that is lower than that of the collector region.

Abstract: A plurality of trenches is provided in a stripe shape extending in a direction parallel to a substrate front surface to a predetermined depth in a depth direction. A gate electrode is provided inside each trench, with a gate insulating film interposed there between. In mesa regions separated by the trenches, p-Type base regions at an emitter potential are provided over the entire surface layer on the substrate front surface side. Inside the p-type base regions, n+-type emitter regions are provided dispersedly at a predetermined interval in the longitudinal direction of the trenches. A p-type collector layer and an n+-type buffer layer are provided in this order on the surface layer of the substrate back surface. The thickness of the n+-type buffer layer is substantially equal to or larger than the thickness of an n?-type drift layer. As a result, switching losses are reduced while maintaining an ON voltage.