Abstract: An accumulation layer has a function of reducing an ON voltage (Von), which is a voltage between the collector and the emitter when turning on the IGBT, by accumulating carrier. However, when turning off the IGBT, the carrier contributes to a turn-off loss (Eoff). A semiconductor device is provided, comprising: a semiconductor substrate, wherein the semiconductor substrate includes: trench portions, a mesa portion each provided between two adjacent trench portions, and a drift layer, wherein the trench portions include: a gate trench portion, and a dummy trench portion, wherein the mesa portion has: an emitter region, a contact region, and a accumulation layer, wherein the number of accumulation layers provided in a depth direction in the mesa portion adjacent to the gate trench portion is larger than that of the accumulation layers provided in the depth direction in the mesa portion between the two dummy trench portions.

Abstract: Provided is a semiconductor device, wherein at least one mesa portion contacting a gate trench portion thereof comprises: a first conductivity type emitter region with a doping concentration higher than a drift region, exposed on the top of the substrate and contacting the gate trench portion; a second conductivity type base region under the emitter region, contacting the trench portion, having a first peak in a doping concentration distribution in a depth direction of the substrate; a first conductivity type accumulation region under the base region, having a doping concentration higher than the drift region; and a second conductivity type intermediate region at a depth position between the base region and the accumulation region, having at least one of a second peak and a kink portion from the first peak to a depth position of a bottom of the trench portion in the doping concentration distribution in the depth direction.

Abstract: A semiconductor device having a contact trench is provided. The semiconductor device including: a semiconductor substrate; a drift region of the first conductivity type provided on an upper surface side of the semiconductor substrate; a base region of the second conductivity type provided above the drift region; a source region of the first conductivity type provided above the base region; two or more trench portions provided penetrating through the source region and the base region from an upper end side of the source region; a contact trench provided in direct contact with the source region between adjacent trench portions; and a contact layer of the second conductivity type provided below the contact trench, is provided. A peak of a doping concentration of the contact layer is positioned shallower than a position of a lower end of the source region.

Abstract: A semiconductor device includes: a first conductivity-type semiconductor substrate; a second conductivity-type base region provided on a front surface side inside the semiconductor substrate, a gate trench portion provided inside the semiconductor substrate and penetrating the base region from a front surface of the semiconductor substrate, the gate trench portion having a gate conductive portion, and a dummy trench portion provided inside the semiconductor substrate and penetrating the base region from a front surface of the semiconductor substrate, the dummy trench portion including an upper dummy conductive portion having an emitter potential and a lower gate conductive portion positioned below the upper dummy conductive portion and having a gate potential, wherein the lower gate conductive portion of the dummy trench portion is connected to the gate conductive portion of the gate trench portion.

Abstract: A semiconductor device is provided, which includes a semiconductor substrate, a transistor section and a diode section. Each of the transistor and diode sections includes a plurality of trench parts, an insulating portion formed on an inner wall of each trench part, a conductive portion provided in each trench part, a plurality of mesa parts, an interlayer dielectric film having contact holes, and a first electrode in contact with the mesa parts via the contact holes. The mesa parts in the transistor section include T-side mesa parts arranged closest to the diode section, the mesa parts in the diode section include D-side mesa parts arranged closest to the transistor section, and a maximum mesa width of mesa parts electrically connected to the first electrode in the transistor section is greater than both a mesa width of the T-side mesa parts and a mesa width of the D-side mesa parts.

Abstract: A semiconductor device is provided, including: a first conductivity-type drift region formed in the semiconductor substrate; a second conductivity-type base region formed between the upper surface of the semiconductor substrate and the drift region; a first conductivity-type accumulation region formed between the drift region and the base region and having a higher doping concentration than the drift region; and a dummy trench portion formed to penetrate the base region from the upper surface of the semiconductor substrate, wherein at least one of the accumulation region and the dummy trench portion has a suppressing structure that suppresses formation of a second conductivity-type inversion layer in a first conductivity-type region adjacent to the dummy trench portion.

Abstract: A semiconductor device is provided that includes: an edge termination portion provided in the peripheral portion of a semiconductor substrate; and an active portion surrounded by the edge termination portion, wherein the active portion includes: a plurality of gate trench portions arrayed along a predetermined array direction; a plurality of dummy trench portions provided between a gate trench portion closest to the edge termination portion among the plurality of gate trench portions and the edge termination portion; mesa regions located between each of the plurality of dummy trench portions; and accumulation regions with a first conductivity-type provided in at least a part of the mesa regions.

Abstract: In order to reduce electric field concentration in a semiconductor device including a main transistor section and a sense transistor section, the semiconductor device is provided, the semiconductor device including a semiconductor substrate of a first conductivity type, a main transistor section in an active region on the semiconductor substrate, and a sense transistor section outside the active region on the semiconductor substrate, wherein the active region is provided with a main well region of a second conductivity type, and wherein the sense transistor section has a sense gate trench section formed extending from the outside of the active region to the main well region on the front surface of the semiconductor substrate.

Abstract: A semiconductor device including a semiconductor substrate, a transistor section provided on the substrate, and a diode section provided on the substrate, the diode and transistor sections arranged in a predetermined arrangement direction, is provided. The diode section includes a first conductivity-type drift region provided in the substrate; a second conductivity-type base region in contact with an upper surface of the substrate and provided above the drift region; first cathode regions of a first conductivity-type separated from each other and second cathode regions separated from each other and having a conductivity type different from that of the first cathode regions, the first and second cathode regions being in contact with a lower surface of the substrate and provided below the drift region; and second conductivity-type floating regions separated from each other and distributed to all the first cathode regions, and arranged to at least partially overlap the first cathode regions.

Abstract: A semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction.

Abstract: A doping concentration distribution in an accumulation region in a depth direction of a semiconductor substrate has a maximum portion at which a doping concentration reaches a maximum value, an upper gradient portion in which the concentration decreases from the maximum portion to a base region, and a lower gradient portion in which the concentration decreases from the maximum portion to a drift region. When a full width at half maximum determined by setting a depth position of the maximum portion as a range of impurity implantation with reference to a range-full width at half maximum characteristic according to a material of the substrate and a type of impurities contained in the accumulation region is set as a standard full width at half maximum, a full width at half maximum of the distribution in the accumulation region is 2.2 times the standard full width at half maximum or greater.

Abstract: A semiconductor device includes: a semiconductor substrate having a first conductivity-type drift region; a transistor portion; and a diode portion, wherein the transistor portion and the diode portion each have: a second conductivity-type base region; a plurality of trench portions penetrating the base region and having conductive portions provided therein; and a mesa portion sandwiched by trench portions, the transistor portion has one or more first conductivity-type accumulation regions that have doping concentrations higher than that of the drift region, the diode portion has one or more first conductivity-type high concentration regions that have doping concentrations higher than that of the drift region, and an integrated concentration of the doping concentrations of the accumulation regions is higher than an integrated concentration of the doping concentrations of the one or more high concentration regions of the mesa portion of the diode portion.

Abstract: A semiconductor device is provided, the semiconductor device including: a semiconductor substrate having a first-conductivity-type drift region; one or more transistor portions provided in the semiconductor substrate; and one or more diode portions provided in the semiconductor substrate, wherein both the transistor portions and the diode portions have trench portions that lie from a top surface of the semiconductor substrate to the drift region and include conductive portions, and in a top view of the semiconductor substrate, a main direction of the trench portions in the transistor portions is different from a main direction of the trench portions in the diode portions.

Abstract: A semiconductor device is provided, including: a first conductivity-type drift region formed in the semiconductor substrate; a second conductivity-type base region formed between the upper surface of the semiconductor substrate and the drift region; a first conductivity-type accumulation region formed between the drift region and the base region and having a higher doping concentration than the drift region; and a dummy trench portion formed to penetrate the base region from the upper surface of the semiconductor substrate, wherein at least one of the accumulation region and the dummy trench portion has a suppressing structure that suppresses formation of a second conductivity-type inversion layer in a first conductivity-type region adjacent to the dummy trench portion.

Abstract: An RC-IGBT having a transistor portion and diode portion is provided. An RC-IGBT having a transistor portion and diode portion, and including: a semiconductor substrate; drift region of the first conductivity type provided on the upper surface side of the semiconductor substrate; base region of the second conductivity type provided above the drift region; source region of the first conductivity type provided above the base region; and two or more trench portions provided passing through the source region and the base region from the upper end side of the source region is provided. The diode portion includes: a source region; contact trench provided between two adjacent trench portions of the two or more trench portions on the upper surface side of the semiconductor substrate; and contact layer of the second conductivity type provided below the contact trench, whose doping concentration is higher than a doping concentration of the base region.

Abstract: An ultrasonic probe includes: a piezoelectric element that transmits and receives an ultrasonic wave; one or a plurality of acoustic matching layers disposed on a subject side of the piezoelectric element; and a conductor layer that applies a voltage to the piezoelectric element, wherein the conductor layer is disposed between the piezoelectric element and the acoustic matching layer, or between the plurality of acoustic matching layers, a magnitude of an acoustic impedance of the conductor layer is between a magnitude of an acoustic impedance of a layer disposed on one surface side of the conductor layer and a magnitude of an acoustic impedance of a layer disposed on the other surface side of the conductor layer, and the conductor layer has a Vickers hardness (Hv) of 50 or more and 600 or less.

Abstract: Provided is a semiconductor device comprising: a semiconductor substrate; a gate trench section that is provided from an upper surface to an inside of the semiconductor substrate and extends in a predetermined extending direction on the upper surface of the semiconductor substrate; a mesa section in contact to the gate trench section in an arrangement direction orthogonal the extending direction; and an interlayer dielectric film provided above the semiconductor substrate; wherein the interlayer dielectric film is provided above at least a part of the gate trench section in the arrangement direction; a contact hole through which the mesa section is exposed is provided to the interlayer dielectric film; and a width of the contact hole in the arrangement direction is equal to or greater than a width of the mesa section in the arrangement direction.

Abstract: A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof.

Abstract: A semiconductor device includes: a gate trench portion and a dummy trench portion provided extending in a predetermined direction of extension at the upper surface of the semiconductor substrate; a mesa portion sandwiched by the gate trench portion and the dummy trench portion; an emitter region provided between the upper surface of the semiconductor substrate and the drift region and provided at an upper surface of the mesa portion and adjacent to the gate trench portion; and a contact region provided between the upper surface of the semiconductor substrate and the drift region and provided at the upper surface of the mesa portion and adjacent to the dummy trench portion.

Abstract: Provided is a semiconductor device comprising: a semiconductor substrate; an active section provided in the semiconductor substrate; an edge termination structure section provided between the active section and an outer peripheral edge of the semiconductor substrate on an upper surface of the semiconductor substrate; and an end lifetime control unit that is provided in the semiconductor substrate in the edge termination structure section and is continuous in a range facing at least two or more diode sections arranged in the first direction, wherein the active section includes: a transistor section and the diode sections alternately arranged with the transistor section in a predetermined first direction on the upper surface of the semiconductor substrate.