Abstract: An RF fingerprint signal processing device configured for executing a machine learning algorithm on a plurality of input signals. The RF fingerprint signal processing device includes a receiver-feature determination circuit and a classifying determination circuit. The receiver-feature determination circuit is configured to compute on the plurality of input signals in a neural network. The classifying determination circuit is coupled with the receiver-feature determination circuit, and the classifying determination circuit is configured to send feedback information of a receiver-feature component to the receiver-feature determination circuit. The receiver-feature determination circuit decreases the receiver-feature weight of the neural network. The receiver-feature weight is associated with the receiver-feature component, and the receiver-feature weight which is decreased is applied for computing an output value of the neural network.

Abstract: A multi-shot moulding part structure includes a first structural part, an ink decoration layer, and a second structural part. The first structural part has a first area surface, a second area surface, and a joining surface located on the second area surface. The joining surface is non-parallel to the second area surface. The ink decoration layer is spread on the first area surface and the second area surface, but not on the joining surface. The second structural part is combined with the first structural part and covers the second area surface. The second structural part touches the joining surface. By the second structural part touching the joining surface of the first structural part that is not coated with the ink decoration layer, the structural bonding strength between the first structural part and the second structural part is enhanced.

Abstract: A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.

Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

Abstract: The invention provides a method for improving sarcopenia of a subject in need thereof by using Phellinus linteus, in which the method includes administering an effective dose of composition to the subject, and the composition includes Phellinus linteus (NITE BP-03321 and BCRC 930210) as an effective substance. By using the aforementioned composition including an extract of a fermented product of the Phellinus linteus and/or its derivative, diameters of myotubes, amounts of muscles and muscle muscular endurance can be maintained, thereby improving sarcopenia.

Abstract: A method of wireless signal transmission management includes transmitting a plurality of data packets to tethering equipment from user equipment to tethering equipment, determining a size of each of the plurality of data packets by the tethering equipment, designating data packets of the plurality of data packets having a specific range of sizes as control signal packets by the tethering equipment, and prioritizing in transmitting the control signal packets to a cellular network by the tethering equipment.

Abstract: A slurry monitoring device, a CMP system and a method of in-line monitoring a slurry are provided. The slurry monitoring device incudes a slurry metrology cell, a plurality of light sources and at least one optical detector. The slurry metrology cell is configured to accommodating a slurry. The light sources are configured to emit light beams on the slurry in the slurry metrology cell. The light sources include a first light source configured to emit a first light beam having a first wavelength, and a second light source configured to emit a second light beam having a second wavelength longer than the first wavelength. The at least one optical detector is configured to detect an intensity of the light beams scattered by abrasive particles in the slurry.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: An electronic device including a substrate, a gate line, a switch element, and a photodetector is provided. The gate line is disposed on the substrate. The switch element is disposed on the substrate and is electrically connected to the gate line. The photodetector is disposed on the substrate and electrically connected to the switch element. The photodetector includes a first semiconductor. In a cross-sectional view of the electronic device, a sidewall of the first semiconductor and the gate line are spaced from each other by a first distance. The first distance is greater than or equal to 2 micrometers and less than or equal to 6 micrometers.

Abstract: An electronic device including a substrate, a first electrode layer, a photodiode, an insulating layer, a second electrode layer, and a first transparent conductive layer is provided. The first electrode layer is disposed on the substrate. The photodiode is disposed on the first electrode layer and is electrically connected to the first electrode layer. The insulating layer is disposed on the photodiode. The second electrode layer is disposed on the insulating layer and is electrically connected to the photodiode. The first transparent conductive layer is disposed on the insulating layer and contacts the second electrode layer. A manufacturing method of an electronic device is also provided.

Abstract: A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.

Abstract: A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.

Abstract: A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: A detection device including a substrate, a conductive pad, a conductive line, a photoelectric element, and an insulating layer is provided. The substrate includes a first region and a second region surrounding the first region. The conductive pad is disposed on the substrate and is located in the second region. The conductive line is disposed on the substrate and extends from the first region to the second region. The conductive line is coupled with the conductive pad. The photoelectric element is disposed on the substrate and is located in the first region. The photoelectric element is coupled to the conductive line. The insulating layer is disposed on the photoelectric element and extends from the first region to the second region. The insulating layer has a groove, and the groove is located in the second region. A manufacturing method of a detection device is also provided.

Abstract: A method includes a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; first and second gate s that cross the first set of active areas along the second direction, the first gate being shared by a first transistor of a first type and a second transistor of a second type and the second gate being shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and coupling at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor. The first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.