Abstract: An IC layout diagram generation system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs. The non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to align a border segment of a cell at a predetermined location relative to a plurality of second metal layer tracks, position the cell relative to a first metal layer cut region alignment pattern based on the plurality of second metal layer tracks, overlap the cell with a first metal layer cut region based on the first metal layer cut region alignment pattern, and generate an IC layout diagram of an IC device based on the cell and the first metal layer cut region.

Abstract: A semiconductor device includes a first group of semiconductor fins arranged at a first fin-to-fin spacing and a second group of semiconductor fins arranged at a second fin-to-fin spacing. The first and second groups of semiconductor fins are separated by a fin-free region larger than the first and second fin-to-fin spacings. The semiconductor device further includes a gate structure extending across the first and second group of semiconductor fins, a Vdd line and a Vss line extending across the gate structure. The first and second groups of semiconductor fins are between the Vdd line and the Vss line from a top view, and an overlapping area between the Vdd line and the first group of semiconductor fins is different from an overlapping area between the Vss line and the second group of semiconductor fins from the top view.

Abstract: A method includes reserving a routing track within a cell, the cell includes signal lines for connection to elements within the cell, the cell further includes a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method includes placing the cell in a chip-level layout, wherein the chip-level layout includes a plurality of power rails. The method includes determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track. The method includes adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.

Abstract: A system (including a processor and memory with computer program code) configured to execute a method which includes generating a layout diagram including: generating first and second active area patterns on opposite sides of (and having long axes parallel to) a first symmetry axis; generating non-overlapping first, second and third conductive patterns (having long axes perpendicular to the first symmetry axis) which overlap the first and second active area patterns; centering the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern for, and which overlaps, central regions of the second and third conductive patterns; centering the first cut-pattern relative to the first symmetry axis; generating a fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to substantially overlap a portion of the first conductive pattern and a portion of the second or third conductive patterns.

Abstract: A method of generating an IC layout diagram includes positioning one or more cells in an IC layout diagram and overlapping the one or more cells with a first metal layer cut region based on a first metal layer cut region alignment pattern. The first metal layer cut region alignment pattern includes a pattern pitch equal to a height of the one or more cells.

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The method further includes arranging at least one first fin feature in the first active region, to obtain a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. At least one of the positioning the first active region or the arranging the at least one first fin feature is executed by a processor.

Abstract: A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.

Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A transmission gate structure includes first and second PMOS transistors in a first active area and first and second NMOS transistors in a second active area. The first and second PMOS transistors include first and second gate structure, the first NMOS transistor includes a third gate structure coupled to the second gate structure, and the second NMOS transistor includes a fourth gate structure coupled to the first gate structure. A first metal zero segment overlies the first active area, a second metal zero segment is offset from the first metal zero segment by an offset distance, a third metal zero segment is offset from the second metal zero segment by the offset distance, and a fourth metal zero segment is offset from the third metal zero segment by the offset distance and overlies the second active area.

Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: An intraoperative nerve evaluation device includes a flexible substrate, and a plurality of detection units disposed on the substrate and spaced apart from one another. Each of the detection units includes an electrode and a conductive wire electrically connected to the electrode. When the electrodes are attached to a nerve, a selected one of the electrodes is configured to receive an input signal via the corresponding conductive wire and to transmit the input signal to the nerve, and each of the electrodes other than the selected one is configured to receive from the nerve a response signal associated with the input signal and to transmit the response signal via the corresponding conductive wire.

Abstract: A semiconductor device includes a semiconductor layered structure, an electrode unit, and an anti-adsorption layer. The electrode unit is disposed on an electrode connecting region of the semiconductor layered structure. The anti-adsorption layer is disposed on a top surface of the electrode unit opposite to the semiconductor layered structure and is electrically connected to the electrode unit. The anti-adsorption layer has an adsorption capacity for at least one of gaseous contaminants and particulate contaminants which is lower than that of the electrode unit. Also disclosed herein is a light-emitting system including the semiconductor device.

Abstract: The disclosure provides a sealing plug assembly including a plug body, a guide ring, a first sealing ring and an elastic component. The plug body has an annular outer surface having a plug side and an exposed side opposite each other and a first annular recess located at the annular outer surface and located between the plug side and the exposed side. The guide ring is sleeved on the plug body and located in the first annular recess. The guide ring has a first inclined surface. The first sealing ring is sleeved on the plug body and located in the first annular recess. The first sealing ring is located farther away from the exposed side of the annular outer surface than the guide ring. The first sealing ring has a second inclined surface matching the first inclined surface. The elastic component is sleeved on the first sealing ring.

Abstract: A system (including a processor and memory with computer program code) configured to execute a method which includes generating a layout diagram including: generating first and second active area patterns on opposite sides of (and having long axes parallel to) a first symmetry axis; generating non-overlapping first, second and third conductive patterns (having long axes perpendicular to the first symmetry axis) which overlap the first and second active area patterns; centering the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern for, and which overlaps, central regions of the second and third conductive patterns; centering the first cut-pattern relative to the first symmetry axis; generating a fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to substantially overlap a portion of the first conductive pattern and a portion of the second or third conductive patterns.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: A method of generating an IC layout diagram includes positioning one or more cells in an IC layout diagram and overlapping the one or more cells with a first metal layer cut region based on a first metal layer cut region alignment pattern. The first metal layer cut region alignment pattern includes a pattern pitch equal to a height of the one or more cells.

Abstract: A method includes reserving a routing track within a cell, the cell includes signal lines for connection to elements within the cell, the cell further includes a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method includes placing the cell in a chip-level layout, wherein the chip-level layout includes a plurality of power rails. The method includes determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track. The method includes adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.