Abstract: A method includes reserving a routing track within a cell, the cell includes signal lines for connection to elements within the cell, the cell further includes a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method includes placing the cell in a chip-level layout, wherein the chip-level layout includes a plurality of power rails. The method includes determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track. The method includes adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The method further includes arranging at least one first fin feature in the first active region, to obtain a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. At least one of the positioning the first active region or the arranging the at least one first fin feature is executed by a processor.

Abstract: A transmission gate structure includes first and second PMOS transistors in a first active area and first and second NMOS transistors in a second active area. The first and second PMOS transistors include first and second gate structure, the first NMOS transistor includes a third gate structure coupled to the second gate structure, and the second NMOS transistor includes a fourth gate structure coupled to the first gate structure. A first metal zero segment overlies the first active area, a second metal zero segment is offset from the first metal zero segment by an offset distance, a third metal zero segment is offset from the second metal zero segment by the offset distance, and a fourth metal zero segment is offset from the third metal zero segment by the offset distance and overlies the second active area.

Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

Abstract: A cell, in a semiconductor device, including: first and second active areas in a semiconductor substrate on opposite sides of the first axis; first, third and fifth, and correspondingly collinear second, fourth and sixth, having long axes in a second direction perpendicular to the first direction; the (A) first, third and fifth, and (B) second, fourth and sixth, conductive structures correspondingly overlapping the second active area; the first and second conductive structures correspondingly being centered between the (C) third and fifth, and (D) fourth and sixth, conductive structures; and a seventh conductive structure; the fourth conductive structure being located over first and second gaps between corresponding ones of the third through sixth, conductive structures; and the fourth conductive structure occupying an area which substantially overlaps one of the first and second conductive structures and a corresponding one of the first and second gaps.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: A semiconductor device includes fins extending substantially parallel to a first direction, at least one of the fins being a dummy fin; and at least one of the fins being an active fin; and at least one gate structure formed over corresponding ones of the fins and extending substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction; wherein the fins and the at least one gate structure are located in a cell region which includes an odd number of fins. In an embodiment, the cell region is substantially rectangular and has first and second edges which are substantially parallel to the first direction; and neither of the first and second edges overlaps any of the fins.

Abstract: A semiconductor device includes: a conductive layer M(h) including first and second power grid (PG) segments and first routing segments which are conductive, where h is an integer and h?1; long axes of the first and second PG segments and the first routing segments extending in a first direction; the first and second PG segments being separated in a second direction by a PG gap having a midpoint, the second direction being substantially perpendicular to the first direction. The first routing segments are distributed: between the first and second PG segments; and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: A method of generating an ECO-layout of an ECO base cell includes: generating first and second active area patterns and arranging them on opposite sides of a first axis; generating non-overlapping first, second and third conductive patterns and arranging each of them so as to correspondingly overlap the first and second active area patterns; locating the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern which overlaps corresponding central regions of the second, and third conductive patterns; aligning the first cut-pattern relative to the first axis; generating a fourth conductive pattern; locating the fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to occupy an area which substantially overlaps a first segment of the first conductive pattern and a first segment of one of the second and third conductive patterns, thereby resulting in the ECO-layout.

Abstract: A cell, in a semiconductor device, including: first and second active areas in a semiconductor substrate on opposite sides of the first axis; first, third and fifth, and correspondingly collinear second, fourth and sixth, having long axes in a second direction perpendicular to the first direction; the (A) first, third and fifth, and (B) second, fourth and sixth, conductive structures correspondingly overlapping the second active area; the first and second conductive structures correspondingly being centered between the (C) third and fifth, and (D) fourth and sixth, conductive structures; and a seventh conductive structure; the fourth conductive structure being located over first and second gaps between corresponding ones of the third through sixth, conductive structures; and the fourth conductive structure occupying an area which substantially overlaps one of the first and second conductive structures and a corresponding one of the first and second gaps.

Abstract: An aircraft galley is provided, including a first galley unit that includes meal carts, cabinets and a countertop-height work area and a second galley unit that includes a countertop-height work area and a plurality of deployable crew seats and with the first galley unit defines a crew work/interaction area. A passenger interaction screen is positioned for viewing by passengers boarding the aircraft and passing through the galley into a passenger cabin. A plurality of lavatories are positioned in a like plurality of corners of the galley and having respective major walls positioned at an oblique angle to a longitudinal axis of the aircraft and with respective doors angled away from the crew work/interaction area.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: An intelligent notification device is provided. The intelligent notification device is adapted to communicate with at least one electronic device. The intelligent notification device includes a detecting device and a controller. The detecting device detects a status parameter of at least one user and an enviromental parameter of the electronic device. The controller is electrically connected to the detecting device to control the electronic device to notify one of a plurality of events in an event schedule according to the event schedule and to dynamically adjust a time sequency of the events in the event schedule according to at least one of the enviromental parameter and the status parameter. An intelligent notification method is further provided.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: An intraoperative nerve evaluation device includes a flexible substrate, and a plurality of detection units disposed on the substrate and spaced apart from one another. Each of the detection units includes an electrode and a conductive wire electrically connected to the electrode. When the electrodes are attached to a nerve, a selected one of the electrodes is configured to receive an input signal via the corresponding conductive wire and to transmit the input signal to the nerve, and each of the electrodes other than the selected one is configured to receive from the nerve a response signal associated with the input signal and to transmit the response signal via the corresponding conductive wire.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A method of generating an ECO-layout of an ECO base cell includes: generating first and second active area patterns and arranging them on opposite sides of a first axis; generating non-overlapping first, second and third conductive patterns and arranging each of them so as to correspondingly overlap the first and second active area patterns; locating the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern which overlaps corresponding central regions of the second, and third conductive patterns; aligning the first cut-pattern relative to the first axis; generating a fourth conductive pattern; locating the fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to occupy an area which substantially overlaps a first segment of the first conductive pattern and a first segment of one of the second and third conductive patterns, thereby resulting in the ECO-layout.

Abstract: A method of manufacturing a solar cell, including providing a patterned silicon wafer having a covered area and an uncovered area, and forming at least one electrode layer in the uncovered area in a low-temperature process.

Abstract: An aircraft galley is provided, including a first galley unit that includes meal carts, cabinets and a countertop-height work area and a second galley unit that includes a countertop-height work area and a plurality of deployable crew seats and with the first galley unit defines a crew work/interaction area. A passenger interaction screen is positioned for viewing by passengers boarding the aircraft and passing through the galley into a passenger cabin. A plurality of lavatories are positioned in a like plurality of corners of the galley and having respective major walls positioned at an oblique angle to a longitudinal axis of the aircraft and with respective doors angled away from the crew work/interaction area.

Abstract: An intelligent notification device is provided. The intelligent notification device is adapted to communicate with at least one electronic device. The intelligent notification device includes a detecting device and a controller. The detecting device detects a status parameter of at least one user and an enviromental parameter of the electronic device. The controller is electrically connected to the detecting device to control the electronic device to notify one of a plurality of events in an event schedule according to the event schedule and to dynamically adjust a time sequency of the events in the event schedule according to at least one of the enviromental parameter and the status parameter. An intelligent notification method is further provided.