Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A semiconductor device includes a semiconductor layered structure, an electrode unit, and an anti-adsorption layer. The electrode unit is disposed on an electrode connecting region of the semiconductor layered structure, and is a multi-layered structure. The anti-adsorption layer is disposed on a top surface of the electrode unit opposite to the semiconductor layered structure. Also disclosed herein is a light-emitting system including the semiconductor device.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A semiconductor device includes a semiconductor layered structure, an electrode unit, and an anti-adsorption layer. The electrode unit is disposed on an electrode connecting region of the semiconductor layered structure. The anti-adsorption layer is disposed on a top surface of the electrode unit opposite to the semiconductor layered structure and is electrically connected to the electrode unit. The anti-adsorption layer has an adsorption capacity for at least one of gaseous contaminants and particulate contaminants which is lower than that of the electrode unit. Also disclosed herein is a light-emitting system including the semiconductor device.

Abstract: A method of manufacturing a transmission gate includes overlying a first active area with a first metal zero segment, the first active area including first and second PMOS transistors, overlying a second active area with a second metal zero segment, the second active area including first and second NMOS transistors, and configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths. At least one of the conductive paths includes a first conductive segment perpendicular to the first and second metal zero segments, and the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.

Abstract: A semiconductor cell structure includes four pairs of conductive segments, a first gate-strip, and a second gate-strip. A first conductive segment is configured to have a first supply voltage, and a second conductive segment is configured to have a second supply voltage. Each of the first gate-strip and the second gate-strip intersects an active zone over a channel region of a transistor. The first gate-strip is conductively connected to the second conductive segment. The semiconductor cell structure also includes a first dummy gate-strip and a second dummy gate-strip. The first dummy gate-strip separates from the first gate-strip by one CPP. The second dummy gate-strip separates from the second gate-strip by one CPP. The first gate-strip and the second gate-strip are separated from each other by two CPPs. The dummy gate-strip and the second dummy gate-strip are separated from each other by four CPPs.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.

Abstract: An integrated circuit is disclosure. The integrated circuit includes a first pair of power rails, a set of conductive lines arranged in the first layer parallel to the first pair of power rails, a first set of active areas. The integrated circuit further includes a first gate arranged along the second direction, between the first pair of power rails, and crossing the first set of active areas in a layout view, wherein the first gate is configured to be shared by a first transistor of a first type and a second transistor of a second type; and a second gate and a third gate, in which the second gate is configured to be a control terminal of a third transistor, and the third gate is configured to be a control terminal of a fourth transistor which is coupled to the control terminal of the third transistor.

Abstract: A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

Abstract: A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h?1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: A method includes generating a layout diagram of a cell of an integrated circuit (IC), and storing the generated layout diagram on a non-transitory computer-readable medium. In the generating the layout diagram of the cell, a first active region is arranged inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is arranged inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region is arranged to overlap the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region.

Abstract: A semiconductor device includes: a conductive layer M(h) including first and second power grid (PG) segments and first routing segments which are conductive, where h is an integer and h?1; long axes of the first and second PG segments and the first routing segments extending in a first direction; the first and second PG segments being separated in a second direction by a PG gap having a midpoint, the second direction being substantially perpendicular to the first direction. The first routing segments are distributed: between the first and second PG segments; and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: A semiconductor device includes fins extending substantially parallel to a first direction, at least one of the fins being a dummy fin; and at least one of the fins being an active fin; and at least one gate structure formed over corresponding ones of the fins and extending substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction; wherein the fins and the at least one gate structure are located in a cell region which includes an odd number of fins. In an embodiment, the cell region is substantially rectangular and has first and second edges which are substantially parallel to the first direction; and neither of the first and second edges overlaps any of the fins.

Abstract: A gas barrier laminate includes an organic layer and an inorganic layered unit. The organic layer includes a product obtained by subjecting a silane compound having an alkoxy group to hydrolysis and condensation. The inorganic layered unit is disposed on the organic layer, and includes an aluminum oxide layer, a hafnium oxide layer, and a silicon aluminum oxide layer that are laminated to one another.

Abstract: A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: The disclosure provides a sealing plug assembly including a plug body, a guide ring, a first sealing ring and an elastic component. The plug body has an annular outer surface having a plug side and an exposed side opposite each other and a first annular recess located at the annular outer surface and located between the plug side and the exposed side. The guide ring is sleeved on the plug body and located in the first annular recess. The guide ring has a first inclined surface. The first sealing ring is sleeved on the plug body and located in the first annular recess. The first sealing ring is located farther away from the exposed side of the annular outer surface than the guide ring. The first sealing ring has a second inclined surface matching the first inclined surface. The elastic component is sleeved on the first sealing ring.