Abstract: A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.

Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Abstract: A receiver circuit is provided on an integrated circuit. The receiver circuit includes first and second power supply terminals, a ground supply terminal, a resistive element coupled between the first and second power supply terminals, and a receiver biased between the second power supply terminal and the ground supply terminal. The receiver draws a bias current through the resistive element, which varies as a positive function with a voltage on the second power supply terminal. The voltage on the second power supply terminal varies as an inverse function of the bias current.

Abstract: A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.

Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.

Abstract: A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.

Abstract: A fault tolerant driver circuit includes a data output driver that receives an enable input and that includes a transistor formed on an isolation well. A well bias circuit provides a first well bias to the isolation well. The well bias circuit includes voltage-controlled impedances that are controlled by a voltage of the data output line, the enable input and a supply voltage. The voltage-controlled impedances connect the first well bias alternatively to: a common conductor through a first impedance when the supply voltage is ON and the enable input is ON; and a second impedance when the supply voltage is on and enable is OFF.

Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Abstract: A CMOS memory element comprising silicon-on-insulator MOSFET transistors is disclosed wherein at least one of the MOSFET transistors is configured such that the body of the transistor is not connected to a voltage source and is instead permitted to electrically float. Implementations of the disclosed memory element with increased immunity to errors caused by heavy ion radiation are also disclosed.

Abstract: A complementary metal-oxide-semiconductor (CMOS) static random-access-memory (SRAM) element comprising a planar metal-insulator-metal (MIM) capacitor is disclosed, and the planar MIM capacitor is electrically connected to the transistors in the CMOS memory element to reduce the effects of charged particle radiation on the CMOS memory element. Methods for immunizing a CMOS SRAM element to the effects of charged particle radiation are also disclosed, along with methods for manufacturing CMOS SRAM including planar MIM capacitors as integrated circuits.

Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Abstract: A method and apparatus are provided for protecting elements of a receiver from overvoltages in a pseudo-differential signal having a true signal and a reference voltage. The method and apparatus limit the true signal to a protection voltage, which is correlated to the reference voltage, to produce a protected true signal. The protected true signal and the reference voltage are applied to inputs of the receiver.

Abstract: A fault tolerant driver circuit includes a data output driver that receives an enable input and that includes a transistor formed on an isolation well. A well bias circuit provides a first well bias to the isolation well. The well bias circuit includes voltage-controlled impedances that are controlled by a voltage of the data output line, the enable input and a supply voltage. The voltage-controlled impedances connect the first well bias alternatively to: a common conductor through a first impedance when the supply voltage is ON and the enable input is ON; and a second impedance when the supply voltage is on and enable is OFF.

Abstract: A method and apparatus are provided for summing DC voltages, which employ at least one native transistor device to add a first DC input voltage to a second DC input voltage to produce a sum output.

Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.

Abstract: A method and apparatus are provided for protecting elements of a receiver from overvoltages in a pseudo-differential signal having a true signal and a reference voltage. The method and apparatus limit the true signal to a protection voltage, which is correlated to the reference voltage, to produce a protected true signal. The protected true signal and the reference voltage are applied to inputs of the receiver.

Abstract: A method and apparatus are provided for summing DC voltages, which employ at least one native transistor device to add a first DC input voltage to a second DC input voltage to produce a sum output.

Abstract: A receiver circuit is provided on an integrated circuit. The receiver circuit includes first and second power supply terminals, a ground supply terminal, a resistive element coupled between the first and second power supply terminals, and a receiver biased between the second power supply terminal and the ground supply terminal. The receiver draws a bias current through the resistive element, which varies as a positive function with a voltage on the second power supply terminal. The voltage on the second power supply terminal varies as an inverse function of the bias current.