Abstract: An electrically programmable floating gate memory cell is gate programmed with tunneling electrons and is not drain erasable. The memory cell comprises a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, a floating gate conductor adjacent to the source and drain regions, a tunnel oxide layer disposed between the floating gate conductor and the source and drain regions, and a control gate conductor adjacent to the floating gate conductor. The source and drain regions each include a high impurity concentration portion and a low impurity concentration portion. The impurity concentration of the low impurity concentration portion is sufficiently low to prevent a substantial threshold voltage variation when a predetermined range of voltages are supplied in a first polarity between the control gate conductor and the drain region.

Abstract: An apparatus and method for storing a momentarily applied binary signal in a non-volatile memory cell and for automatically returning to a state which is indicative of the applied binary signal upon power-up of the non-volatile memory. In one aspect, the non-volatile memory is connected to first and second power busses between which a power source supplies an operating voltage and a programming voltage of a substantially greater magnitude than the operating voltage. The non-volatile memory comprises a memory circuit which is connected between the first and second power busses. The memory circuit includes an input node, an output node, and a non-volatile element which is connected to the input and output nodes. The memory circuit responds to an input binary signal from the input node by latching in a first binary state which is indicative of the input binary signal.

Abstract: An apparatus providing electrostatic discharge (ESD) protection in an input/output transistor. Disposed near the gate and the surface of the substrate is a lightly doped region. A sidewall oxide layer is selectively etched to extend laterally from a gate a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may laterally extend an appreciable amount in that direction. A heavily doped source and drain are implanted in the substrate at areas of the surface exposed by etching, the drain separated from the gate by the significant extent of sidewall oxide. Near the surface of the substrate, the drain is separated from the gate by a similar extent of the lightly doped region, which provides a resistance in series between the drain and gate for ESD protection. The source may also be separated from the gate by a lightly doped region of appreciable extent, which acts as a series resistance between the source and the gate to mitigate ESD.

Abstract: An EEPROM transistor fabricated with a single polysilicon layer. An MOS transistor is fabricated with a subsurface electrode region defined by a stripe in a first direction. A layer of thin oxide is arranged in a second stripe, perpendicular to the first stripe and a polysilicon layer, arranged in a third stripe is disposed over the second stripe of thin oxide. An adjoining parallel plate capacitor is formed by a subsurface region of the same conductivity type as the subsurface electrodes in the first stripe. An insulative second plate of thin oxide is joined to the second stripe and a third plate of the capacitor is formed by a polysilicon plate over the oxide plate. Vertical metallization stripes in the first direction may contact with some components, while parallel metal stripes in a second layer in a perpendicular direction may contact with the remaining members.

Abstract: An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.