Abstract: Techniques are described for fabricating a pair of &bgr;-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. In particular, the lengths of respective channel regions for the transistors are substantially the same, and portions of each gate electrode extending above a channel region include only dopants of a single conductivity type. The techniques can be incorporated into a standard CMOS process.

Abstract: A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.

Abstract: A method and apparatus for manufacturing an electrostatic discharge protection device. A first gate structure for the electrostatic device is formed. A first lightly doped drain and a second lightly doped drain for the electrostatic discharge protection device is formed. A second gate structure for a data path transistor is formed. A third lightly doped drain and a fourth lightly doped drain for a data path transistor is formed, wherein the first lightly doped drain and the second lightly doped drain have a higher doping level relative to the third lightly doped drain and the fourth lightly doped drain.

Abstract: A method and apparatus for manufacturing an electrostatic discharge protection device. A first gate structure for the electrostatic device is formed. A first lightly doped drain and a second lightly doped drain for the electrostatic discharge protection device is formed. A second gate structure for a data path transistor is formed. A third lightly doped drain and a fourth lightly doped drain for a data path transistor is formed, wherein the first lightly doped drain and the second lightly doped drain have a higher doping level relative to the third lightly doped drain and the fourth lightly doped drain.

Abstract: A metal-insulator-metal capacitor is formed between interconnect layers of an integrated circuit with one of the plates of the capacitor formed integrally with one of the interconnect layers. A dielectric layer is formed on top of the interconnect layer, and a top capacitor plate is formed thereon. A bottom plate is defined by the interconnect layer and extends laterally beyond the top plate so that via interconnects may connect to both plates. An intermetal dielectric (IMD) layer separates the interconnect layer and the capacitor from the next interconnect layer above, and the via interconnects are formed through the IMD layer to connect the above interconnect layer to the capacitor plates. The dielectric layer on top of the interconnect layer that defines the bottom plate and another dielectric layer formed on top of the top plate may serve as etch stops for forming the vias for the via interconnects to different levels.

Abstract: An apparatus for determining temperature of a semiconductor wafer during wafer fabrication is disclosed. The semiconductor wafer has a response circuit. The apparatus includes a signal transceiver for (i) transmitting an interrogation signal which excites the response circuit, and (ii) receiving a response signal generated by the response circuit. The apparatus also includes a processing unit electrically coupled to the signal transceiver. The apparatus also includes a memory device electrically coupled to the processing unit. The memory device has stored therein a plurality of instructions which, when executed by the processing unit, causes the processing unit to (a) operate the signal transceiver to (i) transmit the interrogation signal so as to excite the response circuit during fabrication of the semiconductor wafer, and (ii) measure the response signal generated by the response circuit, and (b) determine temperature of the semiconductor wafer based on the response signal of the response circuit.

Abstract: High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

Abstract: A process for oxidizing the silicon layer into a device-isolating field oxide having a radiation-hardened reduced bird's beak. An angled and rotated field implant prior to oxidation is used to increase the doping concentration in the edge region of the MOS transistors to compensate for boron leaching during oxidation. The field oxide is grown at a low temperature by high pressure oxidation which increases total dose hardness by making a silicon-rich oxide film.

Abstract: Techniques are described for fabricating a pair of &bgr;-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. In particular, the lengths of respective channel regions for the transistors are substantially the same, and portions of each gate electrode extending above a channel region include only dopants of a single conductivity type. The techniques can be incorporated into a standard CMOS process.

Abstract: High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well regions of a first conductivity type and well regions of a second conductivity type are formed in the substrate. Low voltage devices are formed in well regions of the first conductivity type. A high voltage device includes source/drain regions of the second conductivity type formed, respectively, in well regions of the second conductivity type, an oxide region disposed on a surface of the substrate located above a region of the substrate that serves as a channel for the high voltage device, and a gate region disposed on the oxide region.

Abstract: A high voltage transistor, formed in a bulk semiconductor material, has a gate region defined by a relatively thick field oxide and a source and drain on opposite sides of the field oxide.

Abstract: The present invention provides a semiconductor protection device in a substrate having a first type of conductivity. The semiconductor protection device includes two vertical bipolar transistors. A well region is located within the substrate having a second type of conductivity with a base region within the well region having a first type of conductivity. A first doped region having the second type of conductivity and a second doped region having a first type of conductivity are located within the well region. A third doped region having the second type of conductivity and a fourth doped region having the first type of conductivity are located within the base region. A doped region having a first type of conductivity is located within the substrate. This doped region is connected to the fourth doped region.

Abstract: High voltage tolerant thin film transistors (TFTs) may be formed during a dual work function polysilicon process used to fabricate poly--poly capacitors with substantially no additional process complexity. Polysilicon lower plate material is patterned in those areas targeted for TFT formation into source, drain, and channel regions. In one embodiment, TFT source and drain regions are doped to the same conductivity as capacitor lower plate regions while TFT channel regions are not doped. In another embodiment, TFT channel regions are lightly doped with positively charged ions. Capacitor dielectric material is used to form TFT gate structures. Capacitor top plate silicon provides TFT gate connection surfaces.

Abstract: A capacitor that is a metal to polysilicon capacitor. The capacitor is fabricated by forming a field oxide layer on a substrate. Then, a polysilicon segment is formed on the field oxide layer. This polysilicon segment forms a polysilicon bottom plate for the capacitor. A dielectric layer is formed and planarized. An opening is made in the dielectric layer to expose a portion of the polysilicon segment. Then, an oxide layer is formed on exposed portions of the polysilicon segment. A metal segment is formed on the oxide layer over the opening, wherein the metal segment forms a top-plate for the semiconductor device.

Abstract: MOS functional devices and electrostatic discharge protection devices are formed on a substrate having a relatively low-resistance area beneath the functional devices to inhibit latch-up of the functional devices and a relatively high resistance area beneath each electrostatic protection device to reduce the snapback holding voltage of each electrostatic discharge protection device.

Abstract: High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

Abstract: An electrically-erasable electrically-programmable read only memory (EEPROM) transistor is programmed and erased by electron tunneling and reduces gate induced drain leakage. The EEPROM transistor comprises a semiconductor substrate having source and drain regions disposed horizontally apart. A floating gate conductor is vertically adjacent to and spaced from the source and drain regions. An insulation layer is disposed between the floating gate conductor and the source and drain regions. A first segment of the insulation layer, which is between the drain region and a minor portion of the floating gate conductor, has a first thickness. A second segment of the insulation layer which is adjacent to the first layer and the remainder on the floating gate conductor, has a second thickness which is substantially greater than the first thickness.

Abstract: The present invention provides a semiconductor protection device in a substrate having a first type of conductivity. The semiconductor protection device includes two vertical bipolar transistors. A well region is located within the substrate having a second type of conductivity with a base region within the well region having a first type of conductivity. A first doped region having the second type of conductivity and a second doped region having a first type of conductivity are located within the well region. A third doped region having the second type of conductivity and a fourth doped region having the first type of conductivity are located within the base region. A doped region having a first type of conductivity is located within the substrate. This doped region is connected to the fourth doped region.

Abstract: A bipolar transistor with a relatively deep emitter region is formed in a BICMOS device using the source/drain mask used to form the source and drain regions of MOSFETs of the device and the base region mask which would otherwise be required in any event to diffuse an emitter region of the bipolar transistor. The emitter is diffused or implanted to a depth greater than the depth to which a source and a drain region of the MOSFET are diffused. By using only the base region and source/drain region masks, and developing in sequence, each of two coatings of photoresist applied on top of one another, an access opening to the emitter region is define solely by the co-location of openings in each of the two coatings, thereby allowing the emitter region to be separately and additionally implanted. The access to the base region for the additional implication is achieved using only a few additional photo-ops and not as a result of using an additional emitter mask.

Abstract: An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.