Patents by Inventor Todd A. Randazzo
Todd A. Randazzo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6931560Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.Type: GrantFiled: August 2, 2001Date of Patent: August 16, 2005Assignee: LSI Logic CorporationInventors: Edson W. Porter, Brian E. Burdick, Todd A. Randazzo, Kevin J. Bruno, Stephen R. Burnham, William K. Petty
-
Patent number: 6924689Abstract: A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value.Type: GrantFiled: June 10, 2002Date of Patent: August 2, 2005Assignee: LSI Logic CorporationInventors: Todd A. Randazzo, E. Wayne Porter
-
Publication number: 20050042818Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.Type: ApplicationFiled: October 6, 2004Publication date: February 24, 2005Inventors: Todd Randazzo, Kenneth Fuchs, John de Walker
-
Patent number: 6855586Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.Type: GrantFiled: November 12, 2003Date of Patent: February 15, 2005Assignee: LSI Logic CorporationInventors: John de Q. Walker, Todd A. Randazzo
-
Patent number: 6825546Abstract: A varactor is formed with a semiconductor junction having a retrograde dopant concentration profile in a depletion region. The retrograde dopant concentration profile results in an approximately linear capacitance/voltage characteristic response of the varactor. The retrograde dopant concentration profile also enables a peak of the dopant concentration to function as a low resistance conductive path connecting to the varactor.Type: GrantFiled: December 28, 2001Date of Patent: November 30, 2004Assignee: LSI Logic CorporationInventors: John Q. Walker, Todd A. Randazzo
-
Patent number: 6822282Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.Type: GrantFiled: April 8, 2003Date of Patent: November 23, 2004Assignee: LSI Logic CorporationInventors: Todd A. Randazzo, Kenneth P. Fuchs, John de Q. Walker
-
Patent number: 6803801Abstract: A level shifter circuit configured for use between a core of a chip and input/output transistor of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.Type: GrantFiled: November 7, 2002Date of Patent: October 12, 2004Assignee: LSI Logic CorporationInventors: Todd Randazzo, Scott Savage, Edson Porter, Matthew Russell, Kenneth Szajda, Hoang Nguyen
-
Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof
Patent number: 6794310Abstract: A method of determining temperature of a semiconductor wafer during wafer fabrication includes the step of providing a response circuit on the semiconductor wafer. The method also includes the step of transmitting an interrogation signal with a signal transceiver so as to excite the response circuit. The method further includes the step of receiving a response signal which was generated by the response circuit as a result of excitation thereof. In addition, the method includes the step of determining temperature of the semiconductor wafer based on the response signal. Moreover, the method includes the step of fabricating a circuit layer on the semiconductor wafer. Both the transmitting step tri and the receiving step are performed contemporaneously with the fabricating step. An apparatus for determining temperature of a semiconductor wafer during wafer fabrication is also disclosed.Type: GrantFiled: September 14, 2001Date of Patent: September 21, 2004Assignee: LSI Logic CorporationInventors: Gayle W. Miller, Todd A. Randazzo -
Publication number: 20040104436Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.Type: ApplicationFiled: November 12, 2003Publication date: June 3, 2004Inventors: John de Q. Walker, Todd A. Randazzo
-
Publication number: 20040090259Abstract: A level shifter circuit configured for use between a core of a chip and input/output transistors of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.Type: ApplicationFiled: November 7, 2002Publication date: May 13, 2004Inventors: Todd Randazzo, Scott Savage, Edson Porter, Matthew Russell, Kenneth Szajda, Hoang Nguyen
-
Patent number: 6710990Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.Type: GrantFiled: January 22, 2002Date of Patent: March 23, 2004Assignee: LSI Logic CorporationInventors: John de Q. Walker, Todd A. Randazzo
-
Publication number: 20030227313Abstract: A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value.Type: ApplicationFiled: June 10, 2002Publication date: December 11, 2003Inventors: Todd A. Randazzo, E. Wayne Porter
-
Publication number: 20030176035Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.Type: ApplicationFiled: April 8, 2003Publication date: September 18, 2003Applicant: LSI Logic CorporationInventors: Todd A. Randazzo, Kenneth P. Fuchs, John de Q. Walker
-
Patent number: 6621299Abstract: An integrated circuit having input output buffers, where the integrated circuit is powered by at least a core power supply and an input output power supply. A level shifter receives an active low signal that indicates that the core power supply has powered down. The level shifter then outputs a known state upon receipt of the active low signal. A control circuit receives the known state form the level shifter, and then tristates the input output buffers upon receipt of the known state.Type: GrantFiled: May 4, 2001Date of Patent: September 16, 2003Assignee: LSI Logic CorporationInventors: Todd A. Randazzo, Matthew J. Russell, Kenneth S. Szajda, Jonathan A. Schmitt, Kenneth G. Richardson, Timothy P. McGonagle
-
Patent number: 6614283Abstract: In an integrated circuit, a voltage level shifter transitions an input signal at a first voltage level to an output signal at a second voltage level. The voltage level shifter generally includes switching elements, such as transistors, that control switching the output signal between logical zero and logical one values. The switching elements have a maximum voltage below which they can operate. The maximum voltage is less than the second voltage level. The voltage across the switching elements is limited to less than the maximum voltage.Type: GrantFiled: April 19, 2002Date of Patent: September 2, 2003Assignee: LSI Logic CorporationInventors: Peter Joseph Wright, Venkatesh P. Gopinath, Todd A. Randazzo
-
Publication number: 20030137789Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.Type: ApplicationFiled: January 22, 2002Publication date: July 24, 2003Inventors: John de Q. Walker, Todd A. Randazzo
-
Patent number: 6596579Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.Type: GrantFiled: April 27, 2001Date of Patent: July 22, 2003Assignee: LSI Logic CorporationInventors: Todd A. Randazzo, Kenneth P. Fuchs, John de Q. Walker
-
Patent number: 6587322Abstract: A method and apparatus for manufacturing an electrostatic discharge protection device. A first gate structure for the electrostatic device is formed. A first lightly doped drain and a second lightly doped drain for the electrostatic discharge protection device is formed. A second gate structure for a data path transistor is formed. A third lightly doped drain and a fourth lightly doped drain for a data path transistor is formed, wherein the first lightly doped drain and the second lightly doped drain have a higher doping level relative to the third lightly doped drain and the fourth lightly doped drain.Type: GrantFiled: December 20, 2001Date of Patent: July 1, 2003Assignee: LSI Logic CorporationInventor: Todd A. Randazzo
-
Patent number: 6545305Abstract: A capacitor that is a metal to polysilicon capacitor. The capacitor is fabricated by forming a field oxide layer on a substrate. Then, a polysilicon segment is formed on the field oxide layer. This polysilicon segment forms a polysilicon bottom plate for the capacitor. A dielectric layer is formed and planarized. An opening is made in the dielectric layer to expose a portion of the polysilicon segment. Then, an oxide layer is formed on exposed portions of the polysilicon segment. A metal segment is formed on the oxide layer over the opening, wherein the metal segment forms a top-plate for the semiconductor device.Type: GrantFiled: April 14, 2000Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventor: Todd A. Randazzo
-
Publication number: 20030042943Abstract: A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.Type: ApplicationFiled: October 25, 2002Publication date: March 6, 2003Applicant: LSI Logic CorporationInventors: Todd A. Randazzo, Brian E. Burdick, Edson W. Porter