Patents by Inventor Toru Sugiyama
Toru Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984387Abstract: A first chip includes a first surface, a second surface, a first semiconductor layer including a nitride semiconductor layer, a first electrode pad located at the first surface, a second electrode pad located at the first surface, a first gate pad located at the first surface, and a third electrode pad located at the first surface. A second chip is located on the first surface of the first chip. The second chip includes a third surface facing the first surface of the first chip, a fourth surface, a second semiconductor layer including a channel of a second conductivity type, a fourth electrode pad located at the fourth surface, a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.Type: GrantFiled: March 3, 2022Date of Patent: May 14, 2024Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Toru Sugiyama, Akira Yoshioka, Yasuhiro Isobe
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Patent number: 11948864Abstract: A semiconductor device has a first wiring extending in a first direction on a nitride semiconductor layer. A source electrode is electrically connected to the first wiring and extends in a second direction. A drain electrode extends in the second direction and includes a first and second portion extending in the second direction, spaced from each other in the first direction. An element isolation region is in the second nitride semiconductor layer between the first and second portions. A third portion extends in the second direction on the first and second portions. A gate electrode extends in the second direction on the second nitride semiconductor layer between the source electrode and the drain electrode. The portion includes holes therein aligned with each other along the second direction with the spacing between adjacent holes in the second direction increasing with increasing distance in the second direction from the first wiring.Type: GrantFiled: September 2, 2021Date of Patent: April 2, 2024Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Akira Yoshioka, Hung Hung, Yasuhiro Isobe, Toru Sugiyama, Hitoshi Kobayashi
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Publication number: 20240105826Abstract: A semiconductor device of an embodiment includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a first electrode film provided on the first insulating film, a second electrode film provided on the first electrode film, and a first field plate electrode provided on the second electrode film. A lower end of the first field plate electrode is located on a second surface of the first electrode film, the second surface being in contact with the second electrode film, rather than a first surface of the first electrode film, the first surface being in contact with the first insulating film.Type: ApplicationFiled: March 1, 2023Publication date: March 28, 2024Inventors: Hitoshi KOBAYASHI, Masaaki ONOMURA, Toru SUGIYAMA, Akira YOSHIOKA, Hung HUNG, Hideki SEKIGUCHI, Tetsuya OHNO, Yasuhiro ISOBE
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Publication number: 20240105563Abstract: A semiconductor device includes a nitride semiconductor element, a first diode, and a second diode; the nitride semiconductor element includes a conductive mounting bed, a semiconductor substrate formed on the mounting bed, a first nitride semiconductor layer, a second nitride semiconductor layer, a first major electrode, a second major electrode, a first gate electrode, and a second gate electrode; the first diode includes a first anode electrode electrically connected to the mounting bed, and a first cathode electrode electrically connected to the first major electrode; and the second diode includes a second anode electrode electrically connected to the mounting bed, and a second cathode electrode electrically connected to the second major electrode.Type: ApplicationFiled: March 9, 2023Publication date: March 28, 2024Inventors: Toru SUGIYAMA, Akira YOSHIOKA, Hitoshi KOBAYASHI, Hung HUNG, Yasuhiro ISOBE, Hideki SEKIGUCHI, Tetsuya OHNO, Masaaki ONOMURA
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Publication number: 20240097671Abstract: A semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed in a first substrate that includes GaN. The first drive circuit charges a parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.Type: ApplicationFiled: February 10, 2023Publication date: March 21, 2024Inventors: Toru SUGIYAMA, Noriaki YOSHIKAWA, Yasuhiko KURIYAMA, Akira YOSHIOKA, Hitoshi KOBAYASHI, Hung HUNG, Yasuhiro ISOBE, Tetsuya OHNO, Hideki SEKIGUCHI, Masaaki ONOMURA
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Publication number: 20240088280Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer having a heterojunction, a second semiconductor layer on the first semiconductor layer and having another heterojunction, a drain electrode on the second semiconductor layer, a source electrode provided on the first semiconductor layer, a gate electrode provided on the first semiconductor layer between the drain electrode and the source electrode, and a first insulating film between the gate electrode and the drain electrode covering the first semiconductor layer and the second semiconductor layer. The second semiconductor layer being separated from the gate electrode by a portion of the insulating film. A distance from the second semiconductor layer to the gate electrode is shorter than a distance from the drain electrode to the gate electrode.Type: ApplicationFiled: February 28, 2023Publication date: March 14, 2024Inventors: Hung HUNG, Yasuhiro ISOBE, Akira YOSHIOKA, Toru SUGIYAMA, Hitoshi KOBAYASHI
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Publication number: 20240047533Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.Type: ApplicationFiled: October 20, 2023Publication date: February 8, 2024Inventors: Akira YOSHIOKA, Yasuhiro ISOBE, Hung HUNG, Hitoshi KOBAYASHI, Tetsuya OHNO, Toru SUGIYAMA
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Patent number: 11830916Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.Type: GrantFiled: March 2, 2021Date of Patent: November 28, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Akira Yoshioka, Yasuhiro Isobe, Hung Hung, Hitoshi Kobayashi, Tetsuya Ohno, Toru Sugiyama
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Publication number: 20230373025Abstract: Provided is a method for producing a welded article. The method welds a plurality of members by laser welding or electron beam welding to form a welded portion and produce a welded article having an internal space. The method includes forming the welded portion surrounding the internal space, and at least one of forming an end point portion of the welded portion outside of the welded portion surrounding the internal space, forming the welded portion by moving a laser or an electron beam from the inside to the outside of the outer edge of the plurality of members, forming another welded portion overlapping with the end point portion of the welded portion previously formed, or forming the end point portion of the welded portion in a region surrounded by the welded portion partitioning the internal space.Type: ApplicationFiled: April 28, 2023Publication date: November 23, 2023Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Toru SUGIYAMA
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Publication number: 20230327052Abstract: Provided are an infrared LED element with an emission wavelength of 1000 nm or more, which has improved emission efficiency by enhancing uniformity of light emission in a surface direction. The infrared LED element includes: a support substrate; a reflection layer formed on top of the support substrate; an insulating layer formed on top of the reflection layer; a contact layer formed on top of the insulating layer, the contact layer being made of GaxIn1-xAsyP1-y (0?x<0.33, 0?y<0.Type: ApplicationFiled: August 26, 2021Publication date: October 12, 2023Applicant: Ushio Denki Kabushiki KaishaInventors: Kazuyuki IIZUKA, Toru SUGIYAMA
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Publication number: 20230307504Abstract: A semiconductor device includes a substrate, a first transistor of a depletion type, a second transistor of an enhancement type, and a gate control circuit. The first and second transistors are provided on the substrate and each include a channel region of a first conductivity type. The first and second transistors are connected in series. The channel region of the first transistor includes a nitride semiconductor. The second transistor operates via an inversion layer of a second conductivity type induced in the channel region thereof. The gate control circuit is connected to a gate electrode of the second transistor. The substrate includes a gate terminal and a power supply terminal. The gate terminal is electrically connected to a gate electrode of the first transistor. The power supply terminal is electrically connected to a connection part between the first transistor and the second transistor.Type: ApplicationFiled: September 12, 2022Publication date: September 28, 2023Inventor: Toru SUGIYAMA
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Publication number: 20230290871Abstract: A semiconductor device includes: a drain electrode including a plurality of drain finger parts; a source electrode including a plurality of source finger parts and a Kelvin source part electrically connected with the source finger parts; a sense electrode positioned between a drain finger part and the Kelvin source part, which are next to each other in a particular direction; and a gate electrode positioned between a drain finger part and a source finger part, which are next to each other in the particular direction, and between a drain finger part and the sense electrode, which are next to each other in the particular direction. The sense electrode and the Kelvin source part are electrically connected via a sense resistance due to a spacing between the sense electrode and the Kelvin source part in the particular direction.Type: ApplicationFiled: September 12, 2022Publication date: September 14, 2023Inventors: Toru SUGIYAMA, Akira YOSHIOKA, Hitoshi KOBAYASHI, Masaaki ONOMURA, Yasuhiro ISOBE, Hung HUNG, Hideki SEKIGUCHI, Tetsuya OHNO
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Publication number: 20230272388Abstract: Provided a novel miR-96-5p inhibitor that is more effective than an antisense oligonucleotide against miR-96-5p, and a novel pharmaceutical composition comprising the same. The miR-96-5p inhibitor comprises a peptide nucleic acid moiety comprising a nucleotide sequence complementary to miR-96-5p.Type: ApplicationFiled: July 29, 2021Publication date: August 31, 2023Applicant: TEIKYO UNIVERSITYInventors: Toshio NAKAKI, Koji AOYAMA, Chisato KINOSHITA, Nobuko MATSUMURA, Kazue UTSUMI, Toru SUGIYAMA, Shun-suke MORIYA
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Publication number: 20230231124Abstract: Disclosed is a positive electrode material having inhibited increase in heat release when exposed to high temperature. The positive electrode material of the disclosure comprises a positive electrode active material, a first solid electrolyte and a second solid electrolyte, wherein the positive electrode active material comprises a lithium-containing oxide, the first solid electrolyte comprises Li and X as constituent elements and comprises no S, X is one or more elements selected from the group consisting of F, Cl, Br and I, the second solid electrolyte comprises Li and S as constituent elements, the first solid electrolyte covers at least part of the surface of the positive electrode active material, the second solid electrolyte contacts with the positive electrode active material across the first solid electrolyte, and the average covering thickness of the first solid electrolyte is 104 nm or greater.Type: ApplicationFiled: July 2, 2021Publication date: July 20, 2023Applicants: Toyota Jidosha Kabushiki Kaisha, Panasonic Holdings CorporationInventors: Toru SUGIYAMA, Shinya SHIOTANI, Takeshi USAMI, Akinobu MIYAZAKI, Izuru SASAKI, Norihito FUJINOKI
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Patent number: 11621435Abstract: A battery pack includes a plurality of secondary batteries, and a binding band made of fiber reinforced plastic. The binding band has a braid member formed into a braided state with use of a plurality of bundled bodies, and a reinforcing part made of resin impregnated in the braid member. Each of the bundled bodies includes a plurality of fiber materials that have been bundled together.Type: GrantFiled: September 18, 2020Date of Patent: April 4, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Toru Sugiyama, Fumio Nomizo, Yutaroh Gotoh, Kenta Watanabe
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Publication number: 20230091984Abstract: A nitride semiconductor device includes a conductive substrate, a nitride semiconductor layer on the substrate, first and second pads disposed above the semiconductor layer and connected to the semiconductor layer, first and second electrodes respectively connected to the first and second pads and extending on the semiconductor layer, a first control electrode extending between the first and second electrodes, and a guard ring disposed on the semiconductor layer, connected to the substrate, and surrounding a region in which the first and second pads, the first and second electrodes and the first control electrode are disposed such that a first capacitor is formed by the guard ring and the first pad and a second capacitor is formed by the guard ring and the second pad.Type: ApplicationFiled: February 28, 2022Publication date: March 23, 2023Inventors: Akira YOSHIOKA, Toru SUGIYAMA
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Publication number: 20230080613Abstract: A semiconductor device includes a first terminal, a second terminal, a first chip, and a resistance part. The first chip includes a substrate electrically connected to the second terminal, a nitride semiconductor layer located on the substrate, a first drain electrode located on the nitride semiconductor layer and electrically connected to the first terminal, a first source electrode located on the nitride semiconductor layer and electrically connected to the second terminal, and a substrate capacitance between the first drain electrode and the substrate. The resistance part is connected in series in a path including the substrate capacitance between the first drain electrode and the second terminal.Type: ApplicationFiled: March 2, 2022Publication date: March 16, 2023Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Toru Sugiyama, Akira Yoshioka, Hung Hung, Yasuhiro Isobe, Hitoshi Kobayashi
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Publication number: 20230081850Abstract: A first chip includes a first surface, a second surface, a first semiconductor layer including a nitride semiconductor layer, a first electrode pad located at the first surface, a second electrode pad located at the first surface, a first gate pad located at the first surface, and a third electrode pad located at the first surface. A second chip is located on the first surface of the first chip. The second chip includes a third surface facing the first surface of the first chip, a fourth surface, a second semiconductor layer including a channel of a second conductivity type, a fourth electrode pad located at the fourth surface, a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.Type: ApplicationFiled: March 3, 2022Publication date: March 16, 2023Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Toru SUGIYAMA, Akira YOSHIOKA, Yasuhiro ISOBE
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Publication number: 20230031562Abstract: A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor including a first electrode, a second electrode, and a first control electrode, a normally-on transistor including a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first diode including a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a Zener diode including a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode; a first terminal provided on the semiconductor package, the first terminal being electrically connected to the first electrode; a plurality of second terminals provided on the semiconductor package, the second terminals being electrically connected to the first electrode, and the second terminals being lined up in a first direction; a third terminal provided on tType: ApplicationFiled: October 18, 2022Publication date: February 2, 2023Inventors: Toru Sugiyama, Akira Yoshioka, Hung Hung, Yasuhiro Isobe, Hitoshi Kobayashi, Tetsuya Ohno, Naonori Hosokawa, Masaaki Onomura, Masaaki Iwai
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Patent number: 11541554Abstract: A non-contact transport device includes a deflector having a flange portion provided with a plurality of nozzle grooves extending radially outward and arranged equidistantly in the circumferential direction. The nozzle grooves are each formed to be hollowed with respect to an upper surface of the flange portion so as to have an arc-shaped cross section, and constitute lead-out channels together with a flat surface of a hollow of a body. A pressure fluid is supplied through a first port of the body into the body and flows through the plurality of nozzle grooves to a workpiece holding surface along first and second curved surfaces of the hollow. As a result, the pressure fluid flowing at high speed between the workpiece holding surface and a workpiece generates a suction force exerted toward the body side, whereby the workpiece is suctioned.Type: GrantFiled: February 8, 2021Date of Patent: January 3, 2023Assignee: SMC CORPORATIONInventors: Toru Nakayama, Toru Sugiyama, Masaru Saitoh, Hiroaki Saka