Patents by Inventor Toshio Kobayashi
Toshio Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7981724Abstract: A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a third insulating layer on a surface of each of the semiconductor device and the second insulating layer; a sixth step of mounting a wiring substrate on a surface of each of the semiconductor device and the second insulating layer; a seventh step of forming a via-hole in the second insulating layer and the third insulating layer; and an eighth step of forming a second wiring pattern on a surface of each of the first insulating layer and the second insulating layer.Type: GrantFiled: October 29, 2009Date of Patent: July 19, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Toshio Kobayashi, Tadashi Arai, Takaharu Yamano
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Publication number: 20110165367Abstract: A plurality of thin-wall parts (9a) of a sealant layer (7) are formed in a portion continuously changed in the interval of one sealing part (8) and a gas barrier layer (6) of other laminate film (4). At the inner circumferential side between the adjacent thin-wall parts (9a) and the thin-wall part (9a) at the innermost circumferential side and at the outer circumferential side of the thin-wall part (9a) of the outermost circumferential side, a thick-wall part (9b) of the sealant layer (7) is formed. All of the opposing sealant layers (7) between the two adjacent thin-wall parts (9a) are mutually heated and fused, so that an excellent adiabatic performance is maintained for a long period.Type: ApplicationFiled: September 9, 2009Publication date: July 7, 2011Applicant: Panasonic CorporationInventors: Shinya Kojima, Fumie Horibata, Tomohisa Tenra, Toshio Kobayashi
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Publication number: 20110127656Abstract: In a method of manufacturing a semiconductor-device mounted board, connection terminals are formed on electrode pads on a semiconductor integrated circuit respectively. A first insulating layer is formed to cover the connection terminals. A plate-like medium having a rough surface is disposed on the first insulating layer. The rough surface of the plate-like medium is pressed onto the first insulating layer so that a part of each of the connection terminals is exposed. A semiconductor device is produced by removing the plate-like medium. A second insulating layer is formed to cover side surfaces of the semiconductor device. A wiring pattern is formed to cover surfaces of the first and second insulating layers, the wiring pattern being electrically connected to the exposed connection terminal parts.Type: ApplicationFiled: November 23, 2010Publication date: June 2, 2011Inventors: Toshio KOBAYASHI, Takaharu YAMANO, Takashi KURIHARA
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Patent number: 7915078Abstract: A manufacturing method for a semiconductor device embedded substrate, includes: a first step including: a step of forming a connection terminal on an electrode pad formed on a semiconductor integrated circuit, a step of forming a first insulating layer on the semiconductor integrated circuit, a step of providing a plate-like body on the first insulating layer, a step of exposing a part of the connection terminal, and a step of removing the plate-like body to manufacture a semiconductor device; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; and a fifth step of forming a first wiring pattern electrically connected to the exposed portion on a surface of each of the first insulating layer and the second insulating layer.Type: GrantFiled: October 29, 2009Date of Patent: March 29, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Toshio Kobayashi, Tadashi Arai, Takaharu Yamano
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Patent number: 7901986Abstract: In a wiring substrate according to the present invention, a base wiring board is constructed by stacking a plurality of unit wiring boards each having wiring patterns which enable an electrical connection between upper and lower sides, in a state that the plurality of unit wiring boards are connected to each other via a connection terminal, and a silicon interposer is stacked on the base wiring board via a connection terminal, and a resin portion is filled in a gap between the plurality of unit wiring boards as well as a gap between the base wiring board and the silicon interposer, and a resin portion serves as a substrate which integrates the base wiring board and the silicon interposer.Type: GrantFiled: November 13, 2007Date of Patent: March 8, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Tadashi Arai, Toshio Kobayashi
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Patent number: 7807510Abstract: There are provided the steps of connecting a chip component 13 to a first substrate 10 through a wire 14, providing an electrode 21 on a second substrate 20, attaching, to the first substrate 10, a molding tool 30 having a protruded portion 31 formed corresponding to an array of a bump connecting pad 12 of the first substrate 10 and a cavity 32 formed corresponding to a region in which the chip component 13 is mounted, thereby forming a first sealing resin 34 for sealing the chip component 13 and the wire 14, bonding the electrode 21 to the bump connecting pad 12 through a solder, thereby bonding the first substrate 10 to the second substrate 20, and filling a second filling resin 40 in a clearance portion between the first substrate 10 and the second substrate 20.Type: GrantFiled: May 20, 2008Date of Patent: October 5, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventor: Toshio Kobayashi
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Patent number: 7802384Abstract: An excavation technique for a stratum capable of excavating a submerged stratum such as a layer containing an underground resource by using laser irradiation in liquid is provided. In this technique, a laser beam transmitted through laser transmission means 20 is irradiated in liquid 90 in form of a laser beam having a wavelength with high absorptance of the liquid 90 by laser-induced bubble generation means 35, generating a bubble flow 36, thus excavation of a submerged stratum may be carried out by using a laser-induced destruction effect. Moreover, a laser beam 41 having low absorptance of the liquid 90 is irradiated by laser irradiation means 39 and passed through the bubble flow 36, thereby applying a thermal effect to a stratum to destroy rock and excavate the stratum. The destruction effect and the thermal effect also may be cooperatively worked.Type: GrantFiled: March 16, 2006Date of Patent: September 28, 2010Assignees: Japan Drilling Co., Ltd., Tohoku University, National University Corporation the University of Electro-CommunicationsInventors: Toshio Kobayashi, Kazuyoshi Takayama, Ken-ichi Ueda, Kazuhisa Otomo, Shigehito Uetake
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Patent number: 7754535Abstract: There are provided the steps of connecting a chip component 13 to a first substrate 10 through wire bonding, providing, on a second substrate 20, an electrode 21 having a solder coat 23 with a copper core 22, polishing a portion of the electrode 21 which is to be bonded to the connecting pad 12, thereby exposing the copper core 22 from the solder coat 23, bonding the exposed portion of the copper core 22 to the bump connecting pad 12 by using a flux non-containing conductive paste 30, thereby bonding the substrates 10 and 20 to each other, and filling a sealing resin 40 in a clearance portion between the substrates 10 and 20.Type: GrantFiled: May 20, 2008Date of Patent: July 13, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventor: Toshio Kobayashi
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Publication number: 20100155992Abstract: A mold resin molding method is provided with: providing a semiconductor device including a first wiring board and a second wiring board electrically connected to the first wiring board through a solder ball; providing a metal mold including a die plate which is independently provided to enable an approach/separation to/from the second wiring board; inserting the semiconductor device into a cavity of the metal mold; abutting the die plate on a surface side of the second wiring board through a release film; injecting a mold resin in a void between the first wiring board and the second wiring board while applying a first pressure from the die plate to the second wiring board; and further injecting the mold resin in the void while applying a second pressure which is higher than the first pressure from the die plate to the second wiring board.Type: ApplicationFiled: December 22, 2009Publication date: June 24, 2010Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Nobuyuki Kurashima, Toshio Kobayashi
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Publication number: 20100140713Abstract: A transistor-type protection device includes: a semiconductor substrate; a well of a first-conductivity-type formed in the semiconductor substrate; a source region of a second-conductivity-type formed in the well; a gate electrode formed on the well via a gate insulating film at one side of the source region; plural drain regions of a second-conductivity-type formed apart from each other and respectively separated at a predetermined distance from a well part immediately below the gate electrode film; and a resistive connection part connecting between the plural drain regions with a predetermined electric resistance.Type: ApplicationFiled: November 18, 2009Publication date: June 10, 2010Applicant: SONY CORPORATIONInventors: Tsutomu IMOTO, Toshio KOBAYASHI
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Publication number: 20100112759Abstract: A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a third insulating layer on a surface of each of the semiconductor device and the second insulating layer; a sixth step of mounting a wiring substrate on a surface of each of the semiconductor device and the second insulating layer; a seventh step of forming a via-hole in the second insulating layer and the third insulating layer; and an eighth step of forming a second wiring pattern on a surface of each of the first insulating layer and the second insulating layer.Type: ApplicationFiled: October 29, 2009Publication date: May 6, 2010Applicant: Shinko Electric Industries Co., Ltd.Inventors: Toshio KOBAYASHI, Tadashi Arai, Takaharu Yamano
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Publication number: 20100112804Abstract: A manufacturing method for a semiconductor device embedded substrate, includes: a first step including: a step of forming a connection terminal on an electrode pad formed on a semiconductor integrated circuit, a step of forming a first insulating layer on the semiconductor integrated circuit, a step of providing a plate-like body on the first insulating layer, a step of exposing a part of the connection terminal, and a step of removing the plate-like body to manufacture a semiconductor device; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; and a fifth step of forming a first wiring pattern electrically connected to the exposed portion on a surface of each of the first insulating layer and the second insulating layer.Type: ApplicationFiled: October 29, 2009Publication date: May 6, 2010Applicant: Shinko Electric Industries Co., Ltd.Inventors: Toshio KOBAYASHI, Tadashi ARAI, Takaharu YAMANO
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Publication number: 20100112802Abstract: A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a first wiring pattern on a surface of each of the first insulating layer and the second insulating layer; a sixth step of forming a via-hole from which the first wiring pattern is exposed on the second insulating layer; and a seventh step of forming a second wiring pattern electrically connected on a surface of the second insulating layer.Type: ApplicationFiled: October 29, 2009Publication date: May 6, 2010Applicant: Shinko Electric Industries Co., Ltd.Inventors: Toshio Kobayashi, Tadashi Arai, Takaharu Yamano
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Publication number: 20100028572Abstract: A corrosion-resistant member having a high acid resistance, plasma resistance, and hydrophilicity and a process for producing the corrosion-resistant member are provided. The corrosion-resistant member is obtained by surface-treating an untreated member (a ceramic, a metal) to a surface-treatment with a spray of a superheated water vapor having a temperature of 300 to 1000° C. The corrosion-resistant member may be a member contacting with a processing space in a vapor phase surface process apparatus (e.g., a chamber) for the surface process of a substrate by a vapor phase method such as a PVD, a CVD, or a dry etching.Type: ApplicationFiled: October 2, 2007Publication date: February 4, 2010Applicant: Asahi Tech Co., Ltd.Inventors: Toshio Kobayashi, Yoshimi Morikawa, Koichiro Takayanagi
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Publication number: 20100025081Abstract: A wiring substrate includes a frame-shaped reinforcing plate in which an opening portion is provided in a center portion, an interposer arranged in the opening portion of the reinforcing plate and having such a structure that a wiring layer connected mutually via a through electrode is formed on both surface sides of a substrate respectively, a resin portion filled between a side surface of the interposer and a side surface of the opening portion of the reinforcing plate, and coupling the interposer and the reinforcing plate, and an n-layered (n is an integer of 1 or more) lower wiring layer connected the wiring layer on the lower surface side of the interposer to extend from the interposer to an outer area.Type: ApplicationFiled: June 26, 2009Publication date: February 4, 2010Inventors: Tadashi Arai, Toshio Kobayashi
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Publication number: 20100001179Abstract: An object is to provide a method capable of boring a borehole even when quartz glass or silicon dioxide is deposited as molten dross by laser irradiation. A laser irradiation position of a workpiece is irradiated with a laser having wavelength of 1.2 ?m or longer and a high factor of absorption into liquid, for example, a CO2 laser, from a laser oscillator through liquid. By high pressure generated in an advancing microbubble flow occurring in the liquid, molten dross is scattered. Thus, the processing, such as boring, of the rock is performed.Type: ApplicationFiled: December 18, 2007Publication date: January 7, 2010Applicants: JAPAN DRILLING CO., LTD., TOHOKU UNIVERSITY, JAPAN OIL, GAS AND METALS NATIONAL CORPORATIONInventors: Toshio Kobayashi, Kazuyoshi Takayama, Kiyonobu Ohtani, Satoru Umezu
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Patent number: 7605424Abstract: A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.Type: GrantFiled: August 29, 2007Date of Patent: October 20, 2009Assignee: Sony CorporationInventors: Tsutomu Imoto, Toshio Kobayashi, Takayoshi Kato
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Publication number: 20090126235Abstract: An excavation technique for a stratum capable of excavating a submerged stratum such as a layer containing an underground resource by using laser irradiation in liquid is provided. In this technique, a laser beam transmitted through laser transmission means 20 is irradiated in liquid 90 in form of a laser beam having a wavelength with high absorptance of the liquid 90 by laser-induced bubble generation means 35, generating a bubble flow 36, thus excavation of a submerged stratum may be carried out by using a laser-induced destruction effect. Moreover, a laser beam 41 having low absorptance of the liquid 90 is irradiated by laser irradiation means 39 and passed through the bubble flow 36, thereby applying a thermal effect to a stratum to destroy rock and excavate the stratum. The destruction effect and the thermal effect also may be cooperatively worked.Type: ApplicationFiled: March 16, 2006Publication date: May 21, 2009Applicants: JAPAN DRILLING CO., LTD., TOHOKU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION THE UNIVERSITY OF ELECTROCOMMUNICATIONSInventors: Toshio Kobayashi, Kazuyoshi Takayama, Ken-ichi Ueda, Kazuhisa Otomo, Shigehito Uetake
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Publication number: 20090052150Abstract: There is provided a wiring board. The wiring board includes: a plurality of laminated insulating layers including a first insulating layer, the first insulating layer being either one of an uppermost layer or a lowermost layer; wiring patterns formed in the plurality of insulating layers; external connection pads provided on the first insulating layer; external connection terminals provided on the external connection pads; and a molding resin provided on a surface of the first insulating layer on which the external connection pads are provided, the molding resin having openings from which the external connection pads are exposed. A thickness of the molding resin is set such that the molding resin does not protrude above the external connection terminals.Type: ApplicationFiled: August 22, 2008Publication date: February 26, 2009Applicant: Shinko Electric Industries Co,, LTD.Inventor: Toshio KOBAYASHI
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Publication number: 20090008765Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.Type: ApplicationFiled: December 12, 2006Publication date: January 8, 2009Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa