Abstract: There are provided the steps of connecting a chip component 13 to a first substrate 10 through wire bonding, providing, on a second substrate 20, an electrode 21 having a solder coat 23 coated with a copper core 22, polishing a portion of the electrode 21 which is to be bonded to the connecting pad 12, thereby exposing the copper core 22 from the solder coat 23, bonding the exposed portion of the copper core 22 to the bump connecting pad 12 by using a flux non-containing conductive paste 30, thereby bonding the substrates 10 and 20 to each other, and filling a sealing resin 40 in a clearance portion between the substrates 10 and 20.

Abstract: There are provided the steps of connecting a chip component 13 to a first substrate 10 through a wire 14, providing an electrode 21 on a second substrate 20, attaching, to the first substrate 10, a molding tool 30 having a protruded portion 31 formed corresponding to an array of a bump connecting pad 12 of the first substrate 10 and a cavity 32 formed corresponding to a region in which the chip component 13 is mounted, thereby forming a first sealing resin 34 for sealing the chip component 13 and the wire 14, bonding the electrode 21 to the bump connecting pad 12 through a solder, thereby bonding the first substrate 10 to the second substrate 20, and filling a second filling resin 40 in a clearance portion between the first substrate 10 and the second substrate 20.

Abstract: To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH1), second conductivity type accumulation layer-forming regions (ACLa, ACL2b), second conductivity type regions (S/D1, S/D2), an insulating film (GD0) and a first conductive layer (CL) formed on the inversion layer-forming region (CH1). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH1), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D1, S/D2).

Abstract: A communication monitoring apparatus for monitoring communication data which are transmitted among a plurality of nodes on a network, includes a detecting section for detecting whether or not a shellcode is included in communication data transmitted and received between at least two nodes within the plurality of nodes and a storing section for storing communication data transmitted from the two nodes as being starting points during a predetermined time, when the detecting section detected the shellcode in communication data.

Abstract: A manufacturing method of a semiconductor device is featured by including: a step for forming a bump on an electrode pad by a bonding wire, the electrode pad being formed in an area corresponding to a semiconductor chip of a substrate; a step in which a via hole is formed in a stacked layer-purpose substrate stacked on the substrate, a conductive layer has been formed on a first major plane of the stacked layer-purpose substrate; the via hole reaches from a second major plane of the stacked layer-purpose substrate to the conductive layer; and the via hole is embedded by conductive paste; a step for adhering the stacked layer-purpose substrate through an insulating layer onto the substrate, and for joining the conductive layer to the bump by the conductive paste; and a step for dividing the substrate in separated pieces.

Abstract: In a wiring substrate according to the present invention, a base wiring board is constructed by stacking a plurality of unit wiring boards each having wiring patterns which enable an electrical connection between upper and lower sides, in a state that the plurality of unit wiring boards are connected to each other via a connection terminal, and a silicon interposer is stacked on the base wiring board via a connection terminal, and a resin portion is filled in a gap between the plurality of unit wiring boards as well as a gap between the base wiring board and the silicon interposer, and a resin portion serves as a substrate which integrates the base wiring board and the silicon interposer.

Abstract: A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.

Abstract: A sheet-like fibrous assembly having an inelastic stretchability is intermittently joined to at least one surface of an elastically stretchable sheet. The elastic sheet is elastically stretchable at least 80% in one direction and the fibrous assembly is curved between each pair of binding spots adjacent to each other on the elastic sheet so as to be stretchable in the one direction and comprises ethylene/propylene copolymer, ethylene/propylene/butene copolymer or a mixture of two or more of these copolymers at 100˜10% by weight.

Abstract: A non-volatile semiconductor memory having a memory transistor including a stacked-layer film formed between a semiconductor substrate and a gate electrode and having a charge storage ability, a first conductivity type region of the semiconductor substrate in which a channel is formed under the control of the gate electrode via the stacked-layer film, and two second conductivity type regions formed at the semiconductor substrate sandwiching the first conductivity type region therebetween, the memory transistor having a channel length L which is between channel lengths L1 and L2. with the channel length L1 being estimated as the boundary of occurrence of a short channel effect at the time of a write operation and the channel length L2 the time of a read operation, with the channel length L1 being different from the channel length L2.

Abstract: Component thermoplastic synthetic fiber having inelastic extensibility as well as fiber diameter of 5-20 ?m constituting a fibrous web is obtained by melt spinning a mixture of two or more thermoplastic synthetic resins each having a number-average molecular weight in a range of 20000-150000 at a draft ratio of 200-2300. In the case of the mixture consisting of at least two types of thermoplastic synthetic resin Ra, Rb having number-average molecular weights Ma, Mb, respectively, wherein a ratio Ma/Mb is 1.1 or higher, Ra is of 20-80 wt %, Rb is of 80-20 wt % and a sum of Ra and Rb makes up 50-100 wt % of the mixture.

Abstract: A sputtering apparatus is provided with a DC power supply 1, an inverter 2 that converts DC voltage to AC voltage, a matching circuit 10 that transforms the AC voltage, a rectifier 4 that converts the transformed AC voltage to direct current, and a sputtering load 6. The matching circuit 10 has a transformer 3 that transforms AC voltage from the inverter 2, inductance L provided in series with at least one of the primary winding 31 and secondary winding 32, and a condenser C provided in parallel with at least one of the primary winding 31 and secondary winding 32 through inductance L.

Abstract: A nonvolatile semiconductor memory device includes: a first semiconductor region having first conductivity; a channel formation region in which a channel inversion layer having second conductivity is formed; a second semiconductor region having the second conductivity; a third semiconductor region having the second conductivity; a laminated insulating film formed on the channel formation region; and a control electrode formed on the laminated insulating film. The laminated insulating film includes a first insulating film, a charge storage film, and a second insulating film in order from the channel formation region side. The control electrode extends to above one of the second semiconductor region and the third semiconductor region. The charge storage film present between an extended portion of the control electrode and the second semiconductor region or the third semiconductor region is removed and a portion where the charge storage film is removed is filled with a third insulating film.

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: The magnetoresistance effect element is of a multilayered structure having at least magnetic layers and an intermediate layer of an insulating material, a semiconductor or an antiferromagnetic material against the magnetic layers, and the magnetoresistance effect element has terminals formed at least on the opposite magnetic layers, respectively, so that a current flows in the intermediate layer. The film surfaces of all the magnetic layers constituting the magnetoresistance effect element are opposed substantially at right angles to the recording surface of a magnetic recording medium. Therefore, the area of the magnetic layers facing the recording surface of the magnetic recording medium can be extremely reduced, and thus the magnetic field from a very narrow region of the high-density recorded magnetic recording medium can be detected by the current which has a tunneling characteristic and passes through the intermediate layer.

Abstract: A terminal arrangement of a motor has a terminal base formed with a plurality of terminal pins, the terminal base being fixed detachably on a stator iron core of a motor, terminal pins formed on bobbins, connected electrically with windings wound around the bobbins, a printed circuit board arranged on the stator iron core so as to connect electrically the terminal pins formed on the bobbins with the terminal pins formed on the terminal base, and an end bracket arranged so as to cover the printed circuit board. A hole is formed in the stator iron core, and an earth electrode is projected from the terminal base, and inserted into the hole so as to be connected electrically with the stator iron core, the earth electrode being connected electrically to one of the terminal pins formed on the terminal base. A capacitor motor has a motor having a stator iron core, and a phase advancing capacitor fixed detachably on the stator iron core.

Abstract: The magnetoresistance effect element is of a multilayered structure having at least magnetic layers and an intermediate layer of an insulating material, a semiconductor or an antiferromagnetic material against the magnetic layers, and the magnetoresistance effect element has terminals formed at least on the opposite magnetic layers, respectively, so that a current flows in the intermediate layer. The film surfaces of all the magnetic layers constituting the magnetoresistance effect element are opposed substantially at right angles to the recording surface of a magnetic recording medium. Therefore, the area of the magnetic layers facing the recording surface of the magnetic recording medium can be extremely reduced, and thus the magnetic field from a very narrow region of the high-density recorded magnetic recording medium can be detected by the current which has a tunneling characteristic and passes through the intermediate layer.

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

Abstract: The present invention provides a semiconductor device in which a problem such as a thermal diffusion defect in a hollow wiring technique can be solved. In the semiconductor device, a gap is formed between wirings formed on a substrate, and the gap is filled with a gas having a thermal conductivity equal to or higher than three times that of air at 0° C.

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

Abstract: The magnetoresistance effect element is of a multilayered structure having at least magnetic layers and an intermediate layer of an insulating material, a semiconductor or an antiferromagnetic material against the magnetic layers, and the magnetoresistance effect element has terminals formed at least on the opposite magnetic layers, respectively, so that a current flows in the intermediate layer. The film surfaces of all the magnetic layers constituting the magnetoresistance effect element are opposed substantially at right angles to the recording surface of a magnetic recording medium. Therefore, the area of the magnetic layers facing the recording surface of the magnetic recording medium can be extremely reduced, and thus the magnetic field from a very narrow region of the high-density recorded magnetic recording medium can be detected by the current which has a tunneling characteristic and passes through the intermediate layer.