Patents by Inventor Toshiyuki Fukuda
Toshiyuki Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8330188Abstract: A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality of bumps 23a, 23b, 23c are formed, at least via the protective film 41, only on circuit blocks whose current-carrying ability and threshold voltage do not satisfy predetermined values and which are in need of performance enhancement. The bumps 23a, 23b, 23c impose stresses on the MOS transistors 36, increasing the mobility of the MOS transistors 36 and thereby improving the performance of the semiconductor device 20.Type: GrantFiled: June 22, 2011Date of Patent: December 11, 2012Assignee: Panasonic CorporationInventors: Takayuki Yoshida, Kimihito Kuwabara, Takuma Motofuji, Toshiyuki Fukuda
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Patent number: 8274125Abstract: An insulation is provided in a portion surrounding a light receiving portion in a semiconductor element, and a sealing resin is provided around the insulation, thereby warping the insulation outward when viewed from the light receiving portion to prevent diffuse light from returning to the light receiving portion of the semiconductor element.Type: GrantFiled: February 26, 2009Date of Patent: September 25, 2012Assignee: Panasonic CorporationInventors: Junya Furuyashiki, Noriyuki Yoshikawa, Toshiyuki Fukuda, Toshimasa Itooka, Hiroki Utatsu
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Patent number: 8193091Abstract: The present invention includes a die pad; signal leads, ground connection leads connected to the die pad; a semiconductor chip including electrode pads for grounding; metal thin wires, and an encapsulating resin for encapsulating the die pad and the semiconductor chip and encapsulating the signal leads and the ground connection lead such that lower portions of the signal leads and the ground connection lead are exposed as external terminals. The ground connection lead is connected to the electrode pad for grounding, so that the resin-encapsulated semiconductor device is electrically stabilized. Furthermore, interference between high frequency signals passing through the signal leads can be suppressed by the die pad and the ground connection leads.Type: GrantFiled: June 19, 2002Date of Patent: June 5, 2012Assignee: Panasonic CorporationInventors: Fumihiko Kawai, Toshiyuki Fukuda, Masanori Minamio, Noboru Takeuchi, Shuichi Ogata, Katsushi Tara, Tadayoshi Nakatsuka
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Patent number: 8189641Abstract: The semiconductor device includes: a base; a first mount placed on the bottom of the base; a second mount placed on the top of the base; a first light-emitting element placed on the bottom of the first mount; and a second light-emitting element placed on the top of the second mount for emitting light. The first light-emitting element and the second light-emitting element are placed so that the emission direction of light from the second light-emitting element is at an angle of depression with respect to the emission direction of light from the first light-emitting element and that the emission direction of light from the first light-emitting element and the emission direction of light from the second light-emitting element substantially coincide with each other as viewed from above the base.Type: GrantFiled: August 12, 2009Date of Patent: May 29, 2012Assignee: Panasonic CorporationInventors: Toshiyuki Fukuda, Mitsuhiro Mishima, Isao Hayami
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Patent number: 8178955Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.Type: GrantFiled: April 4, 2011Date of Patent: May 15, 2012Assignee: Panasonic CorporationInventors: Kenichi Itou, Noboru Takeuchi, Shigetoyo Kawakami, Toshiyuki Fukuda
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Patent number: 8159061Abstract: A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal.Type: GrantFiled: February 22, 2010Date of Patent: April 17, 2012Assignee: Panasonic CorporationInventors: Takeshi Kawabata, Toshiyuki Fukuda
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Molded semiconductor device, apparatus for producing the same, and method for manufacturing the same
Patent number: 8125079Abstract: A resin molding mold 20 with a cavity 21 has a resin injection port 29a from which a molding resin 25 is injected toward the cavity 21, and an air release port 30a from which air from the cavity 21 is released during resin injection. Not only the resin injection port 29a but also the air release port 30a is formed in a top surface portion 21a of the cavity 21. Thus, even if a resin burr remains in the resin injection port 29a or the air release port 30a, it can be prevented from adhering to an external terminal 4A provided on a front surface portion 2a of the substrate 2.Type: GrantFiled: June 5, 2007Date of Patent: February 28, 2012Assignee: Panasonic CorporationInventors: Tetsuo Ito, Takayuki Yoshida, Toshiyuki Fukuda, Takao Ochi -
Publication number: 20110291253Abstract: A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal.Type: ApplicationFiled: August 5, 2011Publication date: December 1, 2011Applicant: PANASONIC CORPORATIONInventors: Toshiyuki FUKUDA, Yoshihiro TOMITA, Hisashi UMEDA, Yasutake YAGUCHI
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Publication number: 20110285003Abstract: An optical device is equipped with a light receiving region 16a and a peripheral circuit region 22 located around the light receiving region 16a on a major surface of an light receiving element 11a; electrodes for external connection 15 electrically connected to the peripheral circuit region 22 formed on a back surface opposite to the major surface of the light receiving element 11a; a transparent member 12 covering the light receiving region 16a adhered on the major surface of the light receiving element 11a with a light-transmitting adhesive 13; and a molding resin 14 for coating side surfaces of the transparent member 12 and the major surface of the light receiving element 11a excluding the region covered with the transparent member 12.Type: ApplicationFiled: July 28, 2011Publication date: November 24, 2011Applicant: Panasonic CorporationInventors: KIYOKAZU ITOI, TOSHIYUKI FUKUDA, YOSHIKI TAKAYAMA, TETSUSHI NISHIO, TETSUMASA MARUO
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Publication number: 20110254094Abstract: A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality of bumps 23a, 23b, 23c are formed, at least via the protective film 41, only on circuit blocks whose current-carrying ability and threshold voltage do not satisfy predetermined values and which are in need of performance enhancement. The bumps 23a, 23b, 23c impose stresses on the MOS transistors 36, increasing the mobility of the MOS transistors 36 and thereby improving the performance of the semiconductor device 20.Type: ApplicationFiled: June 22, 2011Publication date: October 20, 2011Applicant: Panasonic CorporationInventors: Takayuki Yoshida, Kimihito Kuwabara, Takuma Motofuji, Toshiyuki Fukuda
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Patent number: 8017418Abstract: A semiconductor image sensor includes: a semiconductor imaging element including an imaging area, a peripheral circuit area, and an electrode area; cylindrical electrodes provided on electrode terminals so as to be electrically connected with an external device; and a transparent resin layer provided on the upper surface of the semiconductor imaging element. The upper surface of each cylindrical electrode and the upper surface of the transparent resin layer are substantially of the same height.Type: GrantFiled: March 4, 2010Date of Patent: September 13, 2011Assignee: Panasonic CorporationInventors: Masanori Minamio, Toshiyuki Fukuda
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Patent number: 8018526Abstract: One end of a flexible substrate is connected to a solid-state image sensing device and the other end constitutes an external connection part in which external lead-out electrodes are provided. A plurality of electronic components are mounted on a mounting part of the flexible substrate. The flexible substrate is bent at a first bent part thereof to make an acute angle with the solid-state image sensing device and also bent at a second bent part thereof to make an acute angle with the external connection part. The two acute angles are alternate angles and the solid-state image sensing device has a cross section of the letter Z.Type: GrantFiled: May 14, 2007Date of Patent: September 13, 2011Assignee: Panasonic CorporationInventors: Masanori Minamio, Yutaka Harada, Yoshiki Takayama, Toshiyuki Fukuda
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Patent number: 8013350Abstract: An optical device is equipped with a light receiving region 16a and a peripheral circuit region 22 located around the light receiving region 16a on a major surface of an light receiving element 11a; electrodes for external connection 15 electrically connected to the peripheral circuit region 22 formed on a back surface opposite to the major surface of the light receiving element 11a; a transparent member 12 covering the light receiving region 16a adhered on the major surface of the light receiving element 11a with a light-transmitting adhesive 13; and a molding resin 14 for coating side surfaces of the transparent member 12 and the major surface of the light receiving element 11a excluding the region covered with the transparent member 12.Type: GrantFiled: January 3, 2008Date of Patent: September 6, 2011Assignee: Panasonic CorporationInventors: Kiyokazu Itoi, Toshiyuki Fukuda, Yoshiki Takayama, Tetsushi Nishio, Tetsumasa Maruo
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Patent number: 8012869Abstract: An aluminum wire is bonded to a silicon electrode by a wedge tool pressing the aluminum wire against the silicon electrode. In this way, a firmly bonded structure is obtained by sequentially stacking aluminum, aluminum oxide, silicon oxide, and silicon.Type: GrantFiled: November 6, 2009Date of Patent: September 6, 2011Assignee: Panasonic CorporationInventors: Masanori Minamio, Hiroaki Fujimoto, Atsuhito Mizutani, Hisaki Fujitani, Toshiyuki Fukuda
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Patent number: 8008766Abstract: A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal.Type: GrantFiled: December 22, 2009Date of Patent: August 30, 2011Assignee: Panasonic CorporationInventors: Takeshi Kawabata, Toshiyuki Fukuda
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Patent number: 7993980Abstract: A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal.Type: GrantFiled: September 15, 2008Date of Patent: August 9, 2011Assignee: Panasonic CorporationInventors: Toshiyuki Fukuda, Yoshihiro Tomita, Hisashi Umeda, Yasutake Yaguchi
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Patent number: 7985988Abstract: A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality of bumps 23a, 23b, 23c are formed, at least via the protective film 41, only on circuit blocks whose current-carrying ability and threshold voltage do not satisfy predetermined values and which are in need of performance enhancement. The bumps 23a, 23b, 23c impose stresses on the MOS transistors 36, increasing the mobility of the MOS transistors 36 and thereby improving the performance of the semiconductor device 20.Type: GrantFiled: September 11, 2007Date of Patent: July 26, 2011Assignee: Panasonic CorporationInventors: Takayuki Yoshida, Kimihito Kuwabara, Takuma Motofuji, Toshiyuki Fukuda
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Publication number: 20110177657Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.Type: ApplicationFiled: April 4, 2011Publication date: July 21, 2011Applicant: PANASONIC CORPORATIONInventors: Kenichi ITOU, Noboru TAKEUCHI, Shigetoyo KAWAKAMI, Toshiyuki FUKUDA
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Patent number: 7952177Abstract: A resin-sealed semiconductor device with built-in heat sink prevents internal bulging and cracking caused by exfoliation of a semiconductor element from the heat sink when the vapor pressure of moisture absorbed into a gap between the semiconductor element and the heat sink rises during mounting of the semiconductor device to a printed circuit board using lead-free solder. By providing a plurality of separated die pads (502) in a mounting area for a semiconductor element (301) and adhering the semiconductor element (301) to the heat sink (105) via the die pads (502), space is opened up between the semiconductor element (301) and the heat sink (105) for sealing resin (304) to run into.Type: GrantFiled: September 11, 2008Date of Patent: May 31, 2011Assignee: Panasonic CorporationInventors: Tomoki Kawasaki, Yuichiro Yamada, Toshiyuki Fukuda, Shuichi Ogata
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Patent number: 7939933Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.Type: GrantFiled: August 7, 2009Date of Patent: May 10, 2011Assignee: Panasonic CorporationInventors: Kenichi Itou, Noboru Takeuchi, Shigetoyo Kawakami, Toshiyuki Fukuda