Patents by Inventor Toshiyuki Fukuda
Toshiyuki Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100091630Abstract: A plurality of parallel rib prototypes are provided on a flat base plate. A plurality of semiconductor elements are placed in each trench between adjacent ones of the rib prototypes, and a transparent member is bonded to each of the semiconductor elements. Electrode pads of the semiconductor elements are wire bonded to connection electrodes. The trenches are then filled with an encapsulating resin. Thereafter, middle portions, in the longitudinal direction, of the rib prototypes are cut with a dicing saw, and adjacent ones of the semiconductor elements are separated from each other, thereby obtaining semiconductor devices.Type: ApplicationFiled: March 10, 2008Publication date: April 15, 2010Inventors: Junya Furuyashiki, Syouzou Moribe, Hiroki Utatsu, Noriyuki Yoshikawa, Toshiyuki Fukuda, Masanori Minamio, Hiroyuki Ishida
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Publication number: 20100048017Abstract: An aluminum wire is bonded to a silicon electrode by a wedge tool pressing the aluminum wire against the silicon electrode. In this way, a firmly bonded structure is obtained by sequentially stacking aluminum, aluminum oxide, silicon oxide, and silicon.Type: ApplicationFiled: November 6, 2009Publication date: February 25, 2010Applicant: Panasonic CorporationInventors: Masanori MINAMIO, Hiroaki FUJIMOTO, Atsuhito MIZUTANI, Hisaki FUJITANI, Toshiyuki FUKUDA
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Patent number: 7667313Abstract: A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal.Type: GrantFiled: July 24, 2006Date of Patent: February 23, 2010Assignee: Panasonic CorporationInventors: Takeshi Kawabata, Toshiyuki Fukuda
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Publication number: 20100014262Abstract: In a module with embedded electronic components, connection electrodes are formed on the component mounting surface of a substrate. The electrode portions of each of the electronic components are placed on the individual connection electrodes and connected in fixed relation thereto by using a solder. The electronic components are encapsulated in an encapsulating resin.Type: ApplicationFiled: September 24, 2009Publication date: January 21, 2010Applicant: PANASONIC CORPORATIONInventors: Masanori MINAMIO, Hideki TAKEHARA, Yoshiyuki ARAI, Toshiyuki FUKUDA
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Publication number: 20100008203Abstract: A semiconductor element is mounted on a rectangular base of a package including the base and ribs provided on a pair of opposite external edges of the base. Electrode pads of the semiconductor element and connection electrodes provided on rib upper surfaces are connected to each other by metal wires. On the rib upper surfaces, spacers are provided at locations closer to the outside than the connection electrodes. A transparent lid adheres to the upper surfaces of the spacers to cover the entire surface of the package. The height of the spacers is greater than the diameter of the metal wires.Type: ApplicationFiled: March 10, 2008Publication date: January 14, 2010Inventors: Junya Furuyashiki, Syouzou Moribe, Hiroki Utatsu, Noriyuki Yoshikawa, Toshiyuki Fukuda, Masanori Minamio, Hiroyuki Ishida
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Publication number: 20100001174Abstract: In a semiconductor device, a semiconductor element is mounted on a substantially rectangular package. First ribs are respectively provided on a pair of opposite external edges of a mounting surface and project upward from the pair of opposite external edges. External edges of a lid are placed on the upper surfaces of the first ribs, and fixed thereto with an adhesive. Dams are provided on external edges of the first rib upper surfaces. The adhesive is continuously present from side surfaces of the lid to the dams.Type: ApplicationFiled: March 10, 2008Publication date: January 7, 2010Inventors: Junya Furuyashiki, Syouzuo Moribe, Hiroki Utatsu, Noriyuki Yoshikawa, Toshiyuki Fukuda, Masanori Minamio, Hiroyuki Ishida
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Patent number: 7629687Abstract: A semiconductor device includes a wiring board having a plurality of conductive wires aligned on an insulating base material and a board bump with a plated metal formed on each conductive wire so as to cover an upper surface and both sides of the conductive wire; and a semiconductor chip mounted on the wiring board, with electrodes of the semiconductor chip being connected to the conductive wires via the board bumps. Chip bumps are formed on the electrodes of the semiconductor chip. The electrodes of the semiconductor chip are connected to the conductive wires via a bond between the chip bumps and the board bumps. Protruding portions are formed by part of the plated metal of the board bumps at the bonded portion peeling off and protruding outwardly from a bonding surface of the chip bumps and the board bumps. Mechanical damage to the semiconductor chip caused by ultrasonic vibrations applied during process of mounting the semiconductor chip.Type: GrantFiled: October 27, 2006Date of Patent: December 8, 2009Assignee: Panasonic CorporationInventors: Yukihiro Kozaka, Toshiyuki Fukuda, Nozomi Shimoishizaka, Kazuhiko Matsumura
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Patent number: 7629688Abstract: An aluminum wire is bonded to a silicon electrode by a wedge tool pressing the aluminum wire against the silicon electrode. In this way, a firmly bonded structure is obtained by sequentially stacking aluminum, aluminum oxide, silicon oxide, and silicon.Type: GrantFiled: July 24, 2006Date of Patent: December 8, 2009Assignee: Panasonic CorporationInventors: Masanori Minamio, Hiroaki Fujimoto, Atsuhito Mizutani, Hisaki Fujitani, Toshiyuki Fukuda
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Publication number: 20090294950Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.Type: ApplicationFiled: August 7, 2009Publication date: December 3, 2009Applicant: PANASONIC CORPORATIONInventors: Kenichi Itou, Noboru Takeuchi, Shigetoyo Kawakami, Toshiyuki Fukuda
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Patent number: 7606047Abstract: In a module with embedded electronic components, connection electrodes are formed on the component mounting surface of a substrate. The electrode portions of each of the electronic components are placed on the individual connection electrodes and connected in fixed relation thereto by using a solder. The electronic components are encapsulated in an encapsulating resin.Type: GrantFiled: July 19, 2006Date of Patent: October 20, 2009Assignee: Panasonic CorporationInventors: Masanori Minamio, Hideki Takehara, Yoshiyuki Arai, Toshiyuki Fukuda
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Patent number: 7595222Abstract: The semiconductor device includes a first semiconductor chip having first electrodes on a fringe region of a main surface thereof, and a second semiconductor chip smaller in area than the first semiconductor chip and having second electrodes on a main surface thereof. The first semiconductor chip and the second semiconductor chip are connected together by bonding a surface of the second semiconductor chip that is opposite to the main surface thereof to a region of the main surface of the first semiconductor chip other than the fringe region. The first electrodes are connected to the second electrodes by wirings formed over the main surface of the first semiconductor chip, a side surface of the second semiconductor chip and the main surface of the second semiconductor chip.Type: GrantFiled: February 15, 2005Date of Patent: September 29, 2009Assignee: Panasonic CorporationInventors: Nozomi Shimoishizaka, Toshiyuki Fukuda
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Patent number: 7595540Abstract: A semiconductor device including a package (2) having a plurality of wall portions (9a) and a plurality of conductor portions (4), a semiconductor element such as a solid-state image pickup device (1) mounted in an internal space of the base, thin metal wires (5) electrically connecting the semiconductor element and the conductor portions (4) between the wall portions (9a), a resin sealing material (7) implanted in the spaces between the wall portions (9a), and a closing member such as a cover glass (6). The region for connecting the thin metal wires (5) and the wall portion (9a) region overlap each other, so that the device can be reduced in size and in height. The cover glass (6) can not move easily from the correct position because the wall portions (9a) serve as supporting columns, thereby improving the yield.Type: GrantFiled: July 18, 2006Date of Patent: September 29, 2009Assignee: Panasonic CorporationInventors: Toshiyuki Fukuda, Eizou Fujii, Yutaka Fukai, Yutaka Harada, Kiyokazu Itoi
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Patent number: 7589404Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.Type: GrantFiled: June 5, 2008Date of Patent: September 15, 2009Assignee: Panasonic CorporationInventors: Kenichi Itou, Noboru Takeuchi, Shigetoyo Kawakami, Toshiyuki Fukuda
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Patent number: 7586183Abstract: A semiconductor module is formed by alternately stacking resin boards and sheet members. Each of the resin boards includes first buried conductors. A semiconductor chip is mounted on the upper face of each of the resin boards. Each of the sheet members having an opening for accommodating the semiconductor chip and including second buried conductors electrically connected to the first buried conductors. A first resin board located at the bottom is thicker than second resin boards. Each of the sheet members includes an adhesive member covering the upper and side faces of the semiconductor chip.Type: GrantFiled: April 18, 2006Date of Patent: September 8, 2009Assignee: Panasonic CorporationInventors: Takeshi Kawabata, Motoaki Satou, Toshiyuki Fukuda, Toshio Tsuda, Kazuhiro Nobori, Seiichi Nakatani
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Patent number: 7582944Abstract: An optical apparatus includes an optical device (LED device or semiconductor imaging device) having a photoreceptor/light-emitting region, a peripheral circuit region and an electrode region, a transparent member having a larger light passing through region than the optical device and including, on one surface thereof, protruding electrodes for connection to the optical device, external connection electrodes for connection to a mounting substrate, conductive interconnects for connecting the protruding electrodes and the external connection electrodes, and a transparent adhesive provided between the optical device and the transparent member. In the optical apparatus, one surface of the optical device in which the photoreceptor/light-emitting region is formed and one surface of the transparent member are arrange so as to face to each other and electrodes of the optical device and the protruding electrodes of the transparent member are electrically connected and also adhered by the transparent adhesive.Type: GrantFiled: January 26, 2007Date of Patent: September 1, 2009Assignee: Panasonic CorporationInventors: Toshiyuki Fukuda, Yoshiki Takayama, Masanori Minamio, Tetsushi Nishio, Yutaka Harada
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Patent number: 7563644Abstract: An optical device includes a base, an optical element chip attached to the base, an integrated circuit chip attached onto the back surface of the optical element chip, and a translucent member (window member). A wire is buried within the base, and the wire has an internal terminal portion, an external terminal portion, and a midpoint terminal portion. A pad electrode of the optical element chip is connected to the internal terminal portion through a bump, and a pad electrode of the integrated circuit chip is connected to the midpoint terminal portion through a fine metal wire.Type: GrantFiled: August 14, 2008Date of Patent: July 21, 2009Assignee: Panasonic CorporationInventors: Masanori Minamio, Toshiyuki Fukuda
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Patent number: 7547955Abstract: A semiconductor imaging device includes: a semiconductor imaging element including an imaging region, a peripheral circuit region, and an electrode region, the imaging region including a plurality of micro lenses; a semiconductor package the semiconductor package in which a cavity for mounting the semiconductor imaging element is formed, the semiconductor package including a plurality of internal connection terminals formed inside the periphery of the cavity for being connected with a plurality of electrode terminals of the semiconductor imaging element and a plurality of external connection terminals connected with the internal connection terminals; a fixing member for fixing the semiconductor imaging element to the cavity; and an optical member fixed to the semiconductor package by a sealing member so as to cover the semiconductor imaging element arranged in the cavity. Wherein, a face obtained by connecting vertexes of the micro lenses is formed into a continuous concave curve.Type: GrantFiled: January 31, 2007Date of Patent: June 16, 2009Assignee: Panasonic CorporationInventors: Masanori Minamio, Tomoko Komatsu, Toshiyuki Fukuda
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Publication number: 20090146301Abstract: A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode 9 is formed in a region outside of an element mounting region of a substrate 5. The projected electrode 9 includes a protruding portion that protrudes from the front face of a molding resin portion 10. The distal end of the protruding portion is a flat face 13. In addition, a portion of the projected electrode 9 whose cross section is larger than the protruding portion is positioned inside the molding resin portion 10.Type: ApplicationFiled: December 10, 2008Publication date: June 11, 2009Applicant: Panasonic CorporationInventors: Yoshiaki Shimizu, Yuichiro Yamada, Toshiyuki Fukuda
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Publication number: 20090130801Abstract: There are provided a lead frame including a plurality of first external terminal portions 5 provided on a plane, inner lead portions 6 formed of back surfaces of the respective first external terminal portions and arranged so as to surround a region inside the inner lead portions, and second external terminal portions 7 formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor element 2 flip-chip bonded to the inner lead portions via bumps 3; and an encapsulating resin 4 encapsulating surroundings of the semiconductor element and the inner lead portions. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin.Type: ApplicationFiled: January 16, 2009Publication date: May 21, 2009Applicant: PANASONIC CORPORATIONInventors: Toshiyuki FUKUDA, Masanori MINAMIO, Hiroaki FUJIMOTO, Ryuichi SAHARA, Kenichi ITOU
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Publication number: 20090091013Abstract: A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal.Type: ApplicationFiled: September 15, 2008Publication date: April 9, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshiyuki Fukuda, Yoshihiro Tomita, Hisashi Umeda, Yasutake Yaguchi