Abstract: Apparatuses, mufti-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract: Apparatuses, mufti-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract: An apparatus may include a first data strobe (DQS) output buffer (OB), a second DQS OB and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal responsive to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.

Abstract: An apparatus may include a first data strobe (DQS) output buffer (OB), a second DQS OB and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal responsive to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.

Abstract: An apparatus may include a first data strobe (DQS) output buffer (OB), a second DQS OB and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal responsive to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory; and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configure d to delay receipt of the column control signals to the memory.

Abstract: A logic circuit includes a setting circuit which holds and outputs setting information, a first flip-flop which holds data written to the setting circuit and outputs it in synchronization with an inputted clock, a second flip-flop which holds a write address for selecting the setting circuit and outputs it in synchronization with the inputted clock, and a third flip-flop which holds write enable which allows writing to the setting circuit and outputs it in synchronization with the inputted clock, wherein the setting circuit includes a fourth flip-flop which holds the setting information in synchronization with a given timing signal, and a fifth flip-flop which holds the output of the third flip-flop and outputs a write clock to the fourth flip-flop as the timing signal in synchronization with the inputted clock.

Abstract: A logic circuit includes a setting circuit which holds and outputs setting information, a first flip-flop which holds data written to the setting circuit and outputs it in synchronization with an inputted clock, a second flip-flop which holds a write address for selecting the setting circuit and outputs it in synchronization with the inputted clock, and a third flip-flop which holds write enable which allows writing to the setting circuit and outputs it in synchronization with the inputted clock, wherein the setting circuit includes a fourth flip-flop which holds the setting information in synchronization with a given timing signal, and a fifth flip-flop which holds the output of the third flip-flop and outputs a write clock to the fourth flip-flop as the timing signal in synchronization with the inputted clock.

Abstract: A three dimensional integrated circuit includes a master circuit, a slave circuit, and a through-silicon via (TSV). The master circuit is configured to receive and process an input data, a data strobe signal (DQS) and an input command to output a writing data signal to a master die. The through-silicon via (TSV) is electrically coupled between the master circuit and the slave circuit. The master circuit is configured to transfer the writing data signal to a slave die through the TSV. Furthermore, a method for controlling a three dimensional integrated circuit is disclosed herein.

Abstract: A three dimensional integrated circuit includes a master circuit, a slave circuit, and a through-silicon via (TSV). The master circuit is configured to receive and process an input data, a data strobe signal (DQS) and an input command to output a writing data signal to a master die. The through-silicon via (TSV) is electrically coupled between the master circuit and the slave circuit. The master circuit is configured to transfer the writing data signal to a slave die through the TSV. Furthermore, a method for controlling a three dimensional integrated circuit is disclosed herein.

Abstract: Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.

Abstract: A data buffer section stores input words, and outputs them to a first signal line group in order. An error checking and correcting code is generated that has the same number of bits as the words. Some bits are not to be output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups. A code transmission section outputs the error checking and correcting code to different signal lines of the second signal line group respectively, such that a plurality of bits in a code word are not output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups.

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract: An optical receiving apparatus with frame synchronization technology which makes it easy to activate a frame synchronization established state even if bit errors are produced over a transmission link. The apparatus includes: an optoelectrical converting circuit; a pre-stage synchronizing word detecting circuit; a decoder; a post-stage frame synchronization detecting circuit; and a receiver frame synchronization display output circuit.

Abstract: If the number of bits at which 64-bit width data has changed at the same time has exceeded a threshold, the data is outputted, with the polarity of each bit inverted. Otherwise, the data is outputted. A 7-bit width error correcting code is given to the outputted data and the inversion instruction signal indicating whether the number of the changed bits has exceeded the threshold. Error code correction is performed for the data and the inversion instruction signal with the use of the transmitted error correcting code. If the inversion instruction signal for which the error code correction has been performed indicates that the number of the changed bits has exceeded the threshold, the data for which the error code correction has been performed is outputted, with the polarity of each bit inverted. Otherwise, the data for which the error code correction has been performed is outputted.

Abstract: Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.