Abstract: An oscilator circuit for a integrated circuit memory device to optimize the refresh operating circuit and suppress wasteful power consumption in which the oscillator frequency is set high during high temperatures and the oscillator frequency is set low during low temperatures. A current I1 is generated by means of the current source 100a having characteristics in which it is increased during high temperatures and decreased during low temperatures, and is supplied to the ring oscillator 200.

Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. A data line-word line imbalance generates large noise when the data lines are subjected to amplification, which is highly likely to invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

Abstract: A frame synchronization detecting circuit is provided which is capable of efficiently reducing power consumption in a hunting state.

Abstract: When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ).

Abstract: Described herein is a dynamic memory. An N channel type voltage clamp MOSFET is provided which has a drain supplied with a supply voltage supplied from an external terminal, a gate to which a boosted constant voltage is applied, and a source which outputs a constant voltage. The clamp voltage outputted from the source of the voltage clamp MOSFET is supplied to a common source line for each of P channel type amplification MOSFETs constituting a sense amplifier via a P channel type first power MOSFET switch-controlled by a sense amplifier activation signal, as a voltage for operating the sense amplifier. Further, the constant voltage outputted from the source of the voltage clamp MOSFET is supplied to an N-well region in which the P channel type first power MOSFET and the P channel type MOSFETs constituting the sense amplifier are formed, as a bias voltage.

Abstract: Controlling the timing for the overdrive of the sense amplifiers in response to the wiring length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines.

Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.

Abstract: A semiconductor integrated circuit is provided in which a differential amplifier circuit such as a sense amplifier is operated at high speed even if the operating voltage is reduced. To achieve this, a MOS transistor for supplying the operating voltage to a drive line on the high-potential side of a differential amplifier circuit is of N-channel type and the amplitude of a switching control signal for controlling this transistor is the potential of the step-up voltage produced by stepping up a supply voltage in level. The output voltage of an internal step-up circuit for achieving a word-line selection level is utilizable as the step-up voltage.

Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.

Abstract: A semiconductor integrated circuit capable of preventing the excessive overdriving of sense amplifiers when the supply voltage fed thereto is raised. The integrated circuit has differential amplifiers for amplifying a potential difference on complementary signal lines, and a control circuit for generating a first driving control signal for supplying the differential amplifiers with a first driving voltage as an overdriving power supply therefor. The control circuit further generates a second driving control signal for supplying the differential amplifiers with a second driving voltage which is activated after the activated first driving control signal is deactivated and which is lower in level than the first driving voltage. The control circuit includes a MOS circuit as a delay circuit composed of MOS transistors for defining a time interval from the time the first driving control signal is activated until the second driving control signal is activated.

Abstract: A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.

Abstract: A device (e.g., a camera) loaded with a film unit operates to detect a characteristic of the film unit, such as the state of an information part of the film unit. The detection result is used as a basis to control the performance of a further operation, such as a phototaking operation or a state-setting operation for the information part.

Abstract: A camera capable of automatic film rewinding into the magazine, comprises an information recording device for recording at least information on use in an information recording portion formed at a predetermined position of the magazine loaded in the magazine chamber of the camera, an information detecting device capable of detecting recorded information of the magazine when it is loaded, a prohibition device for prohibiting the photographing operation in response to a detection signal corresponding to information, indicating that all the film is already used, detected by the information detecting device and control means for controlling the information recording device, information detecting device and prohibition device in such a manner that the detection by the information detecting device is conducted prior to the recording of information of use by the information recording means, and that the photographing operation is prohibited in response to the detection of information indicating that all the film is a

Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.

Abstract: A residue circuit takes weights of even number bits of a dividend as 1 and weights of odd number bits of the dividend as 2. The circuit includes a plurality of adders for summing bits having weight 1 to output weight 1 at a summing output and weight 2 at a carry output, and a plurality of adders for summing bits having weight 2 to output weight 2 at a summing output and weight 1 at a carry output. With these adders, summing of respective bits of the dividend bits are performed taking the weights into account to repeat summing until the number of bits finally becomes 3 bits. Depending upon the pattern of this 3 bits, a remainder is output by a modulus 3 generation circuit.

Abstract: A dynamic RAM is provided using a sense amplifier compensating for the disparities of characteristics for paired MOSFET's. With this arrangement parasitic capacitance of the bit lines can be increased to be at least 20 times the capacitance of the memory cells. Each bit line is bisected by a switch MOSFET and is disconnected thereby as needed. A plurality of sets of memory arrays are furnished, each including a switch MOSFET for interconnecting common source lines to which the sense amplifier is connected. This permits recycling of the charges of the common source lines.

Abstract: A file document image input can have shading removed to produce a deshaded image that is useful for highly efficient compression encoding, to be thereafter stored and transmitted in such efficient encoded form. When the image is retrieved or received, the decoded and deshaded image may have shading returned to it by combining with a shaded template image stored in the template image memory or by synthesizing shading in specified regions. By removing shading from regions, optical character recognition, shading identification or other processing such as smear prevention can be enhanced.

Abstract: A voltage limiter circuit is disposed in a semiconductor IC chip in order to reduce an operating voltage of an internal circuit of a scaled-down element. A small capacitance of a Vcc wiring by the disposition constitutes a resonance circuit together with an inductance of the Vcc wiring. Resonance at the resonance circuit causes large variation of a supply current and noise. An additional capacitance is connected between the Vcc wiring and a Vss wiring in order to suppress the variation and noise. The capacitance is formed by a PN junction and is connected in series to a damping resistance.

Abstract: An image filing apparatus and method for receiving as multivalue data an image corresponding to a document, converting the data to binary image data and storing the binary image data. According to the features of the present invention, pixels of that portion of an input image corresponding to a particular color are extracted, and luminance data expressing monochromatic binary image data and binary image data designating colored portions are stored in different planes. Not only black pixels but also pixels expressed in a particular color such as red are described in the plane for the luminance data. Pixels having a particular color to be expressed in "red" such as red characters are extracted and recorded as "1" in another particular color plane, for example, in R-plane different from the luminance plane. The R-plane is recorded with binary image data; only pixels written in "red" are expressed as "1" there and other pixels as "0".

Abstract: A camera capable of automatic film rewinding into the magazine, comprises an information recording device for recording at least information on use in an information recording portion formed at a predetermined position of the magazine loaded in the magazine chamber of the camera, an information detecting device capable of detecting recorded information of the magazine when it is loaded, a prohibition device for prohibitng the photographing operation in response to a detection signal corresponding to information, indicating that all the film is already used, detected by the information detecting device and a control device for controlling the information recording device, information detecting device and prohibition device in such a manner that the detection by the information detecting device is conducted prior to the recording of information of use by the information recording device, and that the photographing operation is prohibited in response to the detection of information indicating that all the film i