Abstract: A data buffer section stores input words, and outputs them to a first signal line group in order. An error checking and correcting code is generated that has the same number of bits as the words. Some bits are not to be output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups. A code transmission section outputs the error checking and correcting code to different signal lines of the second signal line group respectively, such that a plurality of bits in a code word are not output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups.

Abstract: The code word generation section generates a code word by adding an error checking and correcting code to an word. The conversion section divides the code words into bit strings each including information bits having the same number of bits as that of the word and code bits having the same number of bits as that of the error checking and correction code, and for each of the bit strings, outputs the information bits of the bit string to a first signal line group and outputs the code bits to a second signal line group. When dividing the code words into the bit strings, the code words are divided in such a manner as to satisfy a condition that a plurality of bits of the same code word are not output at the same time on a particular signal line group.

Abstract: While a phase of an output clock signal is varied, an input frame pulse is latched based on the output clock signal. Then, by using an output frame pulse, which is a result of the latching, generation of a racing state, which is caused by the phase relation between the output clock signal and the output frame pulse, is detected. Next, a phase adjustment amount is determined so that the phase of the output clock signal of the moment when the racing state is generated is shifted by a period corresponding to half a cycle of the output clock signal.

Abstract: An optical receiving apparatus with frame synchronization technology which makes it easy to activate a frame synchronization established state even if bit errors are produced over a transmission link. The apparatus includes: an optoelectrical converting circuit; a pre-stage synchronizing word detecting circuit; a decoder; a post-stage frame synchronization detecting circuit; and a receiver frame synchronization display output circuit.

Abstract: An object of the invention of the present patent application is to provide a frame synchronization technique that will not be prone to enter a frame asynchronization state even if a bit error occurs over a transmission path and the technique serves to convert a received optical signal into an electric signal, correct an error of the electric signal so as to cause a frame synchronization establishment state to occur, count the successive number of synchronization words that have bit errors in excess of an allowable value in an error-correction-coded electric signal after the frame synchronization establishment state has occurred, and determine that a frame asynchronization state has occurred when the successive number reaches a predetermined number.

Abstract: A frame synchronization device and a frame synchronization method capable of preventing a malfunction when a frame is synchronized by using a frame synchronization pattern varying sequentially is presented. A bit serial signal at every frame is transmitted sequentially in a shift register composed of flip-flop circuits. When a bit in each of the stages is detected to be coincided with a corresponding bit in a frame synchronization pattern by coincidence circuits, existence of a synchronized frame is determined. Each bit in the synchronization pattern is also inputted into an all-zero detection circuit. If an all-zero state is detected, a first AND circuit does not output a synchronization pattern detecting signal even with a case where coincidence is detected from the coincidence circuits.

Abstract: If the number of bits at which 64-bit width data has changed at the same time has exceeded a threshold, the data is outputted, with the polarity of each bit inverted. Otherwise, the data is outputted. A 7-bit width error correcting code is given to the outputted data and the inversion instruction signal indicating whether the number of the changed bits has exceeded the threshold. Error code correction is performed for the data and the inversion instruction signal with the use of the transmitted error correcting code. If the inversion instruction signal for which the error code correction has been performed indicates that the number of the changed bits has exceeded the threshold, the data for which the error code correction has been performed is outputted, with the polarity of each bit inverted. Otherwise, the data for which the error code correction has been performed is outputted.

Abstract: A communication device includes: a detector for detecting a predetermined number of consecutive identical codes from first data for transmission to generate a bit inversion instruction signal; a data inversion section for inversing at least one bit of the first data when the bit inversion instruction signal is generated; and a transmitter for transmitting the second data to another communication device. The predetermined number is not greater than a specified number of consecutive identical codes in the data transmission system.

Abstract: A PLI n-bit correction circuit extracts a core header (PLI) from a GFP frame with a fixed payload length; compares it with a predetermined expectation value for each bit; calculates the number of inconsistent bits therebetween; and outputs the predetermined expectation value, instead of the core header, when the number of inconsistent bits is equal to or less than n (n is a natural number); or directly outputs the core header when the number of inconsistent bits is greater than n. A decision on establishment of GFP Layer 2 synchronization is made based on the output of the PLI n-bit correction circuit, wherein predetermined processing is executed on a payload of a GFP frame dropping its core header when GFP Layer 2 synchronization is established, whilst the payload is not subjected to predetermined processing and discarded in the event of GFP Layer 2 desynchronization.

Abstract: A digital data transmission system includes a transmission unit and a reception unit. The transmission unit includes: a transmission-side logic section configured to transmit digital data in parallel onto data lines; and a deskew data generating section configured to transmit deskew data onto a deskew signal line. The deskew data includes sample data and parity data for each of line components of the digital data. The reception unit includes: a skew adjusting section configured to perform deskew processing on the digital data recovered from the data transmitted on the data lines based on the deskew data recovered from the data transmitted on the deskew signal line; an error correcting section configured to perform error correction on the recovered digital data subjected to the deskew processing based on the parity data of the recovered deskew data; and a reception-side logic section configured to execute a predetermined process to the recovered digital data subjected to the error correction.

Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

Abstract: A frame pulse signal latch circuit has: a pulse-width expanding unit which outputs a frame pulse signal FPIN having a pulse width longer than a m-clock cycle; a phase adjustment unit which generates a phase-adjusted output clock CLK?; a flip-flop which latches the frame pulse signal FPIN; a racing detection unit which generates signals, which are shifted by one to m clocks with respect to a frame pulse signal FPOUT, and detects a racing state based on a result of an AND operation of the frame pulse signal FPOUT and the clock-shifted signals; and a control unit which sequentially selects and directs different phase adjustment amounts to the phase adjustment unit, determines an optimal phase adjustment amount based on a worst phase adjustment amount of the case in which the racing state is detected, and gives a direction about the optimal phase adjustment amount to the phase adjustment unit.

Abstract: A frame pulse signal latch circuit has: a pulse-width expanding unit which outputs a frame pulse signal FPIN having a pulse width longer than a m-clock cycle; a phase adjustment unit which generates a phase-adjusted output clock CLK?; a flip-flop which latches the frame pulse signal FPIN; a racing detection unit which generates signals, which are shifted by one to m clocks with respect to a frame pulse signal FPOUT, and detects a racing state based on a result of an AND operation of the frame pulse signal FPOUT and the clock-shifted signals; and a control unit which sequentially selects and directs different phase adjustment amounts to the phase adjustment unit, determines an optimal phase adjustment amount based on a worst phase adjustment amount of the case in which the racing state is detected, and gives a direction about the optimal phase adjustment amount to the phase adjustment unit.

Abstract: While a phase of an output clock signal is varied, an input frame pulse is latched based on the output clock signal. Then, by using an output frame pulse, which is a result of the latching, generation of a racing state, which is caused by the phase relation between the output clock signal and the output frame pulse, is detected. Next, a phase adjustment amount is determined so that the phase of the output clock signal of the moment when the racing state is generated is shifted by a period corresponding to half a cycle of the output clock signal.

Abstract: To obtain a frame synchronization device and a frame synchronization method capable of preventing a malfunction when a frame is synchronized by using a frame synchronization pattern varying sequentially. A bit serial signal at every frame is transmitted sequentially in a shift register composed of flip-flop circuits. When a bit in each of the stages is detected to be coincided with a corresponding bit in a frame synchronization pattern by coincidence circuits, existence of a synchronized frame is determined. Each bit in the synchronization pattern is also inputted into an all-zero detection circuit. If an all-zero state is detected, a first AND circuit does not output a synchronization pattern detecting signal even with a case where coincidence is detected from the coincidence circuits.

Abstract: A method and an apparatus for synchronizing and multiplexing asynchronous signals are presented that enable the plurality of asynchronous signals to be processed without increasing the scale of circuitry. Clock phase absorption sections allow respective asynchronous STM-N signals to switch to a system clock signal. In accordance with the system clock signal, a MSOH termination section, a pointer reception section and a memory section carry out MSOH termination processing, frame phase absorption processing and the like in serial on the asynchronous STM-N signals. Synchronous signals thus generated after frame phase absorption are multiplexed through processing of changing pointer values and the like by a pointer transmission section.

Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.

Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.

Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.

Abstract: An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.