Patents by Inventor Tsugio Takahashi
Tsugio Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030142528Abstract: When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ).Type: ApplicationFiled: January 30, 2003Publication date: July 31, 2003Applicant: Hitachi, Ltd.Inventors: Riichiro Takemura, Tomonori Sekiguchi, Katsutaka Kimura, Kazuhiko Kajigaya, Tsugio Takahashi
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Publication number: 20030112042Abstract: An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.Type: ApplicationFiled: December 16, 2002Publication date: June 19, 2003Applicant: Elpida Memory, Inc.Inventor: Tsugio Takahashi
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Publication number: 20030112682Abstract: Disclosed herein is a dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs.Type: ApplicationFiled: December 4, 2002Publication date: June 19, 2003Applicant: Hitachi, Ltd.Inventors: Tomonori Sekiguchi, Kazuhiko Kajigaya, Katsutaka Kimura, Riichiro Takemura, Tsugio Takahashi, Yoshitaka Nakamura
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Publication number: 20030095455Abstract: In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.Type: ApplicationFiled: January 7, 2003Publication date: May 22, 2003Inventors: Chiaki Dono, Tsugio Takahashi, Hiroki Fujisawa, Masanori Isoda
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Patent number: 6563759Abstract: In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register (124, 125) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit (110) and a column decoder (116).Type: GrantFiled: June 4, 2001Date of Patent: May 13, 2003Assignee: Hitachi, Ltd.Inventors: Hideharu Yahata, Masashi Horiguchi, Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura
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Publication number: 20030086329Abstract: A method is disclosed for controlling reading of data that can increase the data transfer rate in an SDRAM of the posted CAS standard. A memory cell array is constituted by two sub-arrays that can be independently activated. When a READ command is received as input one clock cycle after the input of an ACTV command, a row decoder activates, of the two sub-arrays, only the sub-array containing the memory cell that is selected by a row address AX and column address AY, and then carries out the operations for reading data. The present invention thus enables a greater limitation of the areas that must be activated than a semiconductor memory device of the prior art, thereby decreasing the load on the power supply and, when amplifying bit lines, shortening the time for the voltage of bit lines to attain the stipulated voltage, and consequently, increasing the speed of reading data.Type: ApplicationFiled: October 29, 2002Publication date: May 8, 2003Applicant: Elpida Memory, Inc.Inventors: Minoru Ebihara, Tsugio Takahashi, Hiroshi Watanabe
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Patent number: 6538945Abstract: Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier.Type: GrantFiled: January 18, 2002Date of Patent: March 25, 2003Assignees: Hitachi, Ltd., NEC CorporationInventors: Riichiro Takemura, Tsugio Takahashi, Masayuki Nakamura, Ryo Nagai, Norikatsu Takaura, Tomonori Sekiguchi, Shinichiro Kimura
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Patent number: 6538924Abstract: In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.Type: GrantFiled: May 30, 2001Date of Patent: March 25, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Chiaki Dono, Tsugio Takahashi, Hiroki Fujisawa, Masanori Isoda
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Patent number: 6538912Abstract: When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ).Type: GrantFiled: May 7, 2002Date of Patent: March 25, 2003Assignee: Hitachi, Ltd.Inventors: Riichiro Takemura, Tomonori Sekiguchi, Katsutaka Kimura, Kazuhiko Kajigaya, Tsugio Takahashi
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Patent number: 6501672Abstract: A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided, in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides of the sense amplifier array are connected to one another by wiring using the common electrodes.Type: GrantFiled: September 6, 2000Date of Patent: December 31, 2002Assignee: Hitachi, LTDInventors: Tomonori Sekiguchi, Kazuhiko Kajigaya, Katsutaka Kimura, Riichiro Takemura, Tsugio Takahashi, Yoshitaka Nakamura
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Publication number: 20020142534Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data.Type: ApplicationFiled: May 28, 2002Publication date: October 3, 2002Applicant: Hitachi, Ltd.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura, Tsugio Takahashi
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Publication number: 20020126520Abstract: When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ).Type: ApplicationFiled: May 7, 2002Publication date: September 12, 2002Applicant: Hitachi, Ltd.Inventors: Riichiro Takemura, Tomonori Sekiguchi, Katsutaka Kimura, Kazuhiko Kajigaya, Tsugio Takahashi
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Publication number: 20020122344Abstract: Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers.Type: ApplicationFiled: January 18, 2002Publication date: September 5, 2002Inventors: Riichiro Takemura, Tsugio Takahashi, Masayuki Nakamura, Ryo Nagai, Norikatsu Takaura, Tomonori Sekiguchi, Shinichiro Kimura
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Patent number: 6426889Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. A data line-word line imbalance generates large noise when the data lines are subjected to amplification, which is highly likely to invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.Type: GrantFiled: August 8, 2001Date of Patent: July 30, 2002Assignee: Hitachi, Ltd.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura, Tsugio Takahashi
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Patent number: 6400596Abstract: When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ).Type: GrantFiled: November 29, 2000Date of Patent: June 4, 2002Assignee: Hitachi, Ltd.Inventors: Riichiro Takemura, Tomonori Sekiguchi, Katsutaka Kimura, Kazuhiko Kajigaya, Tsugio Takahashi
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Publication number: 20020061015Abstract: In an embodiment of a matrix switch circuit, a group provided with twelve 64-to-1 selectors is arranged by 64 pieces, that is, (12×64) pieces of 64-to-1 selectors are provided. Address information is input to the selector. STS-12 (one frame) in which twelve 8-bit STS-1 (unit data) are serially arrayed is input from 64 pieces of input terminals of the selector. The matrix switch circuit is further provided with a selecting circuit that selects specific unit data in the frame and 64 pieces of 12-to-1 selectors that forms unit data output from the selecting circuit in one frame and outputs it.Type: ApplicationFiled: May 7, 2001Publication date: May 23, 2002Inventor: Tsugio Takahashi
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Patent number: 6351170Abstract: A gated clock type logic circuit is provided in which timing designing for a supply of a clock can be made easy and a period of time required for designing can be shortened. The gated clock type logic circuit has a gate circuit designed to allow a clock signal inputted in accordance with a level of a clock enabling signal to be passed or to be masked. An output of the gate circuit to control a latching timing of a latch circuit for receiving data is fed to a clock input terminal of the latch circuit. The gated clock type logic circuit is provided with a selector which receives an input data and an output data from the latch circuit and selects either of the input data or the output data by using a data enabling signal as a selecting signal and outputs it. An output from the selector is fed to a data input terminal of the latch circuit.Type: GrantFiled: May 30, 2000Date of Patent: February 26, 2002Assignee: NEC CorporationInventors: Tsugio Takahashi, Satomi Horita
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Publication number: 20020015328Abstract: In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.Type: ApplicationFiled: May 30, 2001Publication date: February 7, 2002Inventors: Chiaki Dono, Tsugio Takahashi, Hiroki Fujisawa, Masanori Isoda
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Publication number: 20020003747Abstract: In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register (124, 125) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit (110) and a column decoder (116).Type: ApplicationFiled: June 4, 2001Publication date: January 10, 2002Inventors: Hideharu Yahata, Masashi Horiguchi, Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura
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Publication number: 20010046153Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data.Type: ApplicationFiled: August 8, 2001Publication date: November 29, 2001Applicant: Hitachi, Ltd.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura, Tsugio Takahashi