Abstract: A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.

Abstract: A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two clock signals and detects the phase relationship between the two signals by determining which signal was received first. In response, the phase decision circuit generates respective logic signals to reflect the phase relationship determination. The circuit also includes a latch circuit that receives the logic signals from the phase decision circuit and holds the phase relationship determination of the circuit a predetermined time after a predetermined transition of both clock signals have occurred. Methods and systems are also disclosed.

Abstract: Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.

Abstract: Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether.

Abstract: A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two clock signals and detects the phase relationship between the two signals by determining which signal was received first. In response, the phase decision circuit generates respective logic signals to reflect the phase relationship determination. The circuit also includes a latch circuit that receives the logic signals from the phase decision circuit and holds the phase relationship determination of the circuit a predetermined time after a predetermined transition of both clock signals have occurred. Methods and systems are also disclosed.

Abstract: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.

Abstract: Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a circuit including a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal. The circuit further includes a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.

Abstract: A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.

Abstract: A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty cycle irrespective of the duty cycle of the clock input to the DCC circuit. A DCC initialization scheme selectively activates the frequency division and edge detection operations in the DCC based on the lock status of the DCC during initialization. Upon initialization, the frequency division and edge detection operations are turned off or disabled. After the DCC is properly locked, these operations are enabled to obtain the 50% duty cycle output clock. This approach initializes the reduced-frequency DCC without output glitches, which can affect locking of a DLL with which the DCC may be used. The prevention of instability in locking of the DCC and DLL upon system initialization results in swift establishment of DCC and DLL locks without significant power consumption or loss of clock cycles.

Abstract: A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

Abstract: A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.

Abstract: A method of operating a delay locked loop is comprised of producing a first output signal in response to a first lock point. A new lock point is measured, or otherwise determined, while continuing to produce the first output signal. Thereafter, a second output signal is produced in response to the new lock point. The new lock point data may be loaded into the delay locked loop while the delay locked loop continues to produce the first output signal. The delay locked loop switches from producing the first output signal, responsive to a first lock point, to producing the second output signal, responsive to the new lock point, in response to various conditions such as control signals, e.g. an auto refresh command, a precharge all command, a mode register load command, a power down entry, a power down exit (among others), in response to a timer, e.g., an internal timer (among others), or in response to environmental condition signals, e.g., a temperature sensor output signal (among others).

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: Some embodiments include a delay locked circuit having multiple paths. A first path measures a timing of a first clock signal during a measurement. A second path generates a second clock signal based on the first clock signal. The delay locked circuit periodically performs the measurement to adjust a timing relationship between the first and second clock signals. The time interval between one measurement and the next measurement is unequal to the cycle time of the first clock signal. Additional embodiments are disclosed.

Abstract: A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.

Abstract: A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty cycle irrespective of the duty cycle of the clock input to the DCC circuit. A DCC initialization scheme selectively activates the frequency division and edge detection operations in the DCC based on the lock status of the DCC during initialization. Upon initialization, the frequency division and edge detection operations are turned off or disabled. After the DCC is properly locked, these operations are enabled to obtain the 50% duty cycle output clock. This approach initializes the reduced-frequency DCC without output glitches, which can affect locking of a DLL with which the DCC may be used. The prevention of instability in locking of the DCC and DLL upon system initialization results in swift establishment of DCC and DLL locks without significant power consumption or loss of clock cycles.