Abstract: Methods and apparatuses for testing image sensors are disclosed. Desirable apparatuses of the present invention include image sensor testing devices comprising a digital light projection system capable of projecting static or dynamic images onto an image sensing device under test and an image sensor signal detection means for analyzing the output of said image sensing device under test. The digital light projection system comprises a light source, collimating optics, a digital micromirror device, and focusing optics. Other desirable methods and apparatuses of the present invention include image sensor testing devices employing a digital light projection system capable of simultaneously testing a plurality of image sensors. According to the present invention, the light source is calibrated and converted to a desired test image by the digital micromirror device. The test image is then focused onto an image sensor, the output of which is read by a detector and correlated with the input digital test image.

Abstract: Clock synchronization and skew adjustment circuits are described that utilize varying unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement, allowing a reduced circuit implementation and improved lock characteristics. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical. This allows clock synchronization and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size and power consumption, while having improved lock characteristics over a wide range of frequencies.

Abstract: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.

Abstract: Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the synchronization device. The tuning elements are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single design. The tuning elements may be implemented to provide uniformity in the access time through a range of conditions, such as drain voltages and temperatures.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: A method of operating a delay locked loop is comprised of producing a first output signal in response to a first lock point. A new lock point is measured, or otherwise determined, while continuing to produce the first output signal. Thereafter, a second output signal is produced in response to the new lock point. The new lock point data may be loaded into the delay locked loop while the delay locked loop continues to produce the first output signal. The delay locked loop switches from producing the first output signal, responsive to a first lock point, to producing the second output signal, responsive to the new lock point, in response to various conditions such as control signals, e.g. an auto refresh command, a precharge all command, a mode register load command, a power down entry, a power down exit (among others), in response to a timer, e.g., an internal timer (among others), or in response to environmental condition signals, e.g., a temperature sensor output signal (among others).

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.

Abstract: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.

Abstract: A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.

Abstract: A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: A delay-lock loop includes a phase detector comparing the phase of a digital input signal to the phase of a feedback signal. The phase detector generates a corresponding control signal that is used to control the delay of a delay line. A multiplexer couples the input signal to the input of the delay line and thereafter couples a signal received from the output of the delay line to the input of the delay line so that the delay line functions as several individual delay lines. At least one digital signal that has propagated through the delay line is used as a feedback signal that is coupled from the output of the delay line to the phase detector by a signal router. The phase of the signal coupled to the phase detector by the router is therefore locked to the phase of the input signal.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

Abstract: A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

Abstract: The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system includes input, output, and data storage devices, a processor coupled to the devices, a memory device coupled to the processor, and a configuration circuit interposed between the processor and the memory device to selectively couple lines in the address, control and data busses of the processor to lines in the address, control and data busses of the memory device. In another embodiment, a memory device includes an array coupleable to one or more busses of an external device and a configuration circuit between the array and the busses of the external device to selectively couple the busses to the memory cell array. In a particular embodiment, the configuration circuit includes one or more bi-stable relays, such as Micro-Electrical-Mechanical System (MEMS) relays.