Patents by Inventor Tzu-Jin Yeh
Tzu-Jin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230112936Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.Type: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Inventors: Garming LIANG, Simon CHAI, Tzu-Jin YEH, En-Hsiang YEH, Wen-Sheng CHEN
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Patent number: 11569164Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: GrantFiled: May 21, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 11555848Abstract: A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.Type: GrantFiled: July 15, 2021Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsieh-Hung Hsieh, Yen-Jen Chen, Tzu-Jin Yeh
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Patent number: 11558019Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.Type: GrantFiled: November 4, 2019Date of Patent: January 17, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Garming Liang, Simon Chai, Tzu-Jin Yeh, En-Hsiang Yeh, Wen-Sheng Chen
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Publication number: 20220385251Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: An-Hsun LO, Wen-Sheng CHEN, En-Hsiang YEH, Tzu-Jin YEH
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Publication number: 20220381808Abstract: A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit, each of the plurality of power-amplifier chips being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: HSIEH-HUNG HSIEH, WU-CHEN LIN, YEN-JEN CHEN, TZU-JIN YEH
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Patent number: 11493563Abstract: A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.Type: GrantFiled: October 30, 2019Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsieh-Hung Hsieh, Wu-Chen Lin, Yen-Jen Chen, Tzu-Jin Yeh
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Publication number: 20220336446Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jun-De JIN, Tzu-Jin YEH
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Publication number: 20220328473Abstract: A semiconductor device includes a substrate, a first metal-oxide-semiconductor device and a at least one first resistor. The substrate includes a non-doped region. The first metal-oxide-semiconductor device extends into the substrate. The first metal-oxide-semiconductor device is adjacent to the non-doped region. The at least one first resistor is disposed right above the non-doped region and arranged in a first row aligned with the first metal-oxide-semiconductor device in a first direction.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jun-De JIN, Tzu-Jin YEH
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Patent number: 11456710Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: GrantFiled: October 5, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Hsun Lo, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 11456711Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.Type: GrantFiled: August 31, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: En-Hsiang Yeh, Wen-Sheng Chen, Chia-Ming Liang, Chung-Ho Chai, Zong-You Li, Tzu-Jin Yeh
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Publication number: 20220300694Abstract: A phase shifter includes a first transistor and a second transistor. The first transistor includes a first gate terminal configured to receive a first voltage. The first transistor is configured to adjust at least a resistance or a first capacitance of the phase shifter responsive to the first voltage. The second transistor is coupled to the first transistor. The second transistor includes a second gate terminal configured to receive a second voltage. The second transistor is configured to adjust a second capacitance of the phase shifter responsive to the second voltage. The second gate terminal includes a first polysilicon portion and a second polysilicon portion extending in a first direction. The first polysilicon portion and the second polysilicon portion are positioned along opposite edges of an active region of the first transistor and the second transistor.Type: ApplicationFiled: June 6, 2022Publication date: September 22, 2022Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
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Patent number: 11450769Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.Type: GrantFiled: February 24, 2021Date of Patent: September 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
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Publication number: 20220263464Abstract: An oscillator includes a forward stage including first and second terminals and a transformer-coupled band-pass filter (BPF) coupled between the first and second terminals and including a coupling device between the first and second terminals, and a transformer including first and second windings in a metal layer of an IC. The first winding includes a first conductive structure coupled to the first terminal and a second conductive structure coupled to a voltage node, a third conductive structure including first and second extending portions connected to the first and second conductive structures. The second winding includes a fourth conductive structure including a third extending portion coupled to the voltage node, and a fourth extending portion coupled to the second terminal. The third extending portion is between the second conductive structure and the first extending portion, and the fourth extending portion is between the first conductive structure and the second extending portion.Type: ApplicationFiled: April 25, 2022Publication date: August 18, 2022Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
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Publication number: 20220255504Abstract: A differential oscillator includes a differential circuit and a transformer-coupled band-pass filter (BPF) coupled between first and second output nodes. The BPF includes a coupling device coupled between the output nodes and a transformer including first and second windings in a metal layer of an IC. The first winding includes first and second conductive structures coupled to the first output node and a voltage node, respectively, and a third conductive structure including first and second extending portions connected to the first and second conductive structures, respectively. The second winding includes a fourth conductive structure including a third extending portion coupled to the voltage node and a fourth extending portion coupled to the second output node. The third extending portion is between the second conductive structure and the first extending portion, and the fourth extending portion is between the first conductive structure and the second extending portion.Type: ApplicationFiled: April 28, 2022Publication date: August 11, 2022Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
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Patent number: 11380680Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, first and second wells of a first conductivity type, a third well of a second conductivity type, different from the first conductivity type, a first doped region of the first conductivity type in the second well, a metal-oxide-semiconductor device, and a feature. The metal-oxide-semiconductor device is at least partially disposed within the substrate and includes a gate structure disposed above the first well. The gate structure, the first doped region, or the combination thereof is configured to be floated. The feature is disposed adjacent to the metal-oxide-semiconductor device. The feature extends into the substrate with a first depth and a portion of the metal-oxide-semiconductor device extends into the substrate with a second depth smaller than the first depth.Type: GrantFiled: May 14, 2020Date of Patent: July 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jun-De Jin, Tzu-Jin Yeh
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Patent number: 11354481Abstract: A phase shifter includes an active region, a first and a second set of gates and a set of contacts. The active region extends in a first direction and is located at a first level. The first and second set of gates each extend in a second direction, overlap the active region and are located at a second level. The second set of gates are positioned along opposite edges of the active region, are configured to receive a first voltage, and are part of a first transistor. The first transistor is configured to adjust a first capacitance of the phase shifter responsive to the first voltage. The set of contacts extend in the second direction, are over the active region, are located at a third level, and are positioned between at least the second set of gates.Type: GrantFiled: June 14, 2019Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
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Patent number: 11323068Abstract: In some embodiments, a differential oscillator includes a differential circuit coupled between a first output node and a second output node and a transformer-coupled band-pass filter (BPF). The transformer-coupled BPF is coupled between the first output node and the second output node and includes a coupling device and a transformer. The coupling device is coupled between the first output node and the second output node. The transformer includes a first winding coupled between the first output node and a voltage node and a second winding coupled between the second output node and the voltage node.Type: GrantFiled: April 15, 2021Date of Patent: May 3, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
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Patent number: 11316473Abstract: A band-pass filter (BPF) includes a pair of coupled transformers including first through fourth conductive structures. The first conductive structure includes a first terminal and two first extending portions extending from the first terminal and configured as primary windings. The second conductive structure includes a second terminal and two second extending portions extending from the second terminal. A first via connects the third conductive structure to a first one of the two second extending portions, the third conductive structure and the first one of the two second extending portions thereby being configured as a first secondary winding. A second via connects the fourth conductive structure to a second one of the two second extending portions, the fourth conductive structure and the second one of the two second extending portions thereby being configured as a second secondary winding.Type: GrantFiled: February 11, 2021Date of Patent: April 26, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
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Publication number: 20220069779Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: En-Hsiang Yeh, Wen-Sheng Chen, Chia-Ming Liang, Chung-Ho Chai, Zong-You Li, Tzu-Jin Yeh