Patents by Inventor Tzu-Jin Yeh

Tzu-Jin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor with asymmetric source and drain regions
    Patent number: 10276716
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Dual-mode RF transmission frontend
    Patent number: 10256783
    Abstract: A transmission frontend includes a modulator configured to generate a modulated signal. A first selectable path is electrically coupled to the modulator and is configured to generate a first signal having a first power level. A second selectable path is electrically coupled to the modulator and is configured to generate a second signal having a second power level. The first power level is greater than the second power level. A transformer is electrically coupled to each of the first selectable path and the second selectable path. An antenna is electrically coupled to the transformer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Lin Chu, Hsieh-Hung Hsieh, Tzu-Jin Yeh
  • INTEGRATED CIRCUIT WITH GUARD RING
    Publication number: 20190103354
    Abstract: An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Chiao-Han LEE, Hsien-Yuan LIAO, Ying-Ta LU, Chi-Hsien LIN, Ho-Hsiang CHEN, Tzu-Jin YEH
  • TRANSMITTER CIRCUIT WITH POWER DETECTION
    Publication number: 20190036503
    Abstract: A transmitter circuit includes an amplifier configured to output a radio frequency (RF) signal on an output node, a power detection circuit coupled with the output node and configured to generate an output voltage having a first component based on a power level of the RF signal, and a reference voltage generator configured to generate a reference voltage. A comparator is configured to receive the output voltage and the reference voltage, an analog-to-digital converter (ADC) is coupled between the comparator and the amplifier, and the amplifier is configured to adjust the power level of the RF signal responsive to an output of the ADC.
    Type: Application
    Filed: September 17, 2018
    Publication date: January 31, 2019
    Inventors: Hong-Lin CHU, Hsieh Hung HSIEH, Tzu-Jin YEH
  • Integrated circuit with guard ring
    Patent number: 10163779
    Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Han Lee, Hsien-Yuan Liao, Ying-Ta Lu, Chi-Hsien Lin, Ho-Hsiang Chen, Tzu-Jin Yeh
  • Transmitter power detection circuit and method
    Patent number: 10079583
    Abstract: A circuit includes a first device between a first input node and an internal node, a second device between a second input node and the internal node, a third device between the internal node and ground, a fourth device between the internal node and an output node, and a fifth device between the output node and ground. The second and third devices generate a direct current (DC) voltage on the internal node by dividing a bias voltage on the second input node. The fourth device generates, from the DC voltage, a first component of an output voltage on the output node. The first and third devices generate a modulation signal on the internal node by dividing a radio frequency (RF) signal on the first input node. The fifth device rectifies the modulation signal to generate a second output voltage component.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hong-Lin Chu, Hsieh-Hung Hsieh, Tzu-Jin Yeh
  • DUAL-MODE RF TRANSMISSION FRONTEND
    Publication number: 20180212568
    Abstract: A transmission frontend includes a modulator configured to generate a modulated signal. A first selectable path is electrically coupled to the modulator and is configured to generate a first signal having a first power level. A second selectable path is electrically coupled to the modulator and is configured to generate a second signal having a second power level. The first power level is greater than the second power level. A transformer is electrically coupled to each of the first selectable path and the second selectable path. An antenna is electrically coupled to the transformer.
    Type: Application
    Filed: September 25, 2017
    Publication date: July 26, 2018
    Inventors: Hong-Lin CHU, Hsieh-Hung HSIEH, Tzu-Jin YEH
  • SEMICONDUCTOR DEVICE HAVING A LOW POWER CONSUMPTION
    Publication number: 20180198418
    Abstract: An amplifying unit includes a converter and a feedback mechanism. The converter has a supply input coupled to a supply node. The converter further has an input terminal configured to receive an input signal. The converter is configured to amplify the input signal from the input terminal to generate an output signal. The feedback mechanism is coupled to the input terminal of the converter and is configured to cause a constant bias current to flow from the supply node through the converter based on the input signal.
    Type: Application
    Filed: July 5, 2017
    Publication date: July 12, 2018
    Inventors: An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh, Wen-Sheng Chen
  • System and method for inductive wireless signaling
    Patent number: 9991721
    Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-De Jin, Fan-Ming Kuo, Huan-Neng Chen, Ming-Hsien Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh
  • TRANSMITTER POWER DETECTION CIRCUIT AND METHOD
    Publication number: 20180152161
    Abstract: A circuit includes a first device between a first input node and an internal node, a second device between a second input node and the internal node, a third device between the internal node and ground, a fourth device between the internal node and an output node, and a fifth device between the output node and ground. The second and third devices generate a direct current (DC) voltage on the internal node by dividing a bias voltage on the second input node. The fourth device generates, from the DC voltage, a first component of an output voltage on the output node. The first and third devices generate a modulation signal on the internal node by dividing a radio frequency (RF) signal on the first input node. The fifth device rectifies the modulation signal to generate a second output voltage component.
    Type: Application
    Filed: August 22, 2017
    Publication date: May 31, 2018
    Inventors: Hong-Lin CHU, Hsieh-Hung HSIEH, Tzu-Jin YEH
  • WIRELESS RECEIVER
    Publication number: 20180131332
    Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first trans conductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 10, 2018
    Inventors: An-Hsun LO, Wen-Sheng CHEN, En-Hsiang YEH, Tzu-Jin YEH
  • WIRELESS TRANSMITTER WITH SWITCHABLE MODE
    Publication number: 20180115198
    Abstract: A wireless transmitter includes a an amplifier; and a switchable transformer, coupled to the amplifier, wherein the amplifier is configured to be coupled to the switchable transformer in first and second configurations, wherein the first configuration causes the amplifier to provide a first output impedance to the switchable transformer, and wherein the second configuration causes the amplifier to provide a second output impedance to the switchable transformer, the first and second output impedances being different from each other.
    Type: Application
    Filed: October 20, 2016
    Publication date: April 26, 2018
    Inventors: Wen-Sheng CHEN, An-Hsun LO, En-Hsiang YEH, Tzu-Jin YEH
  • Ultra-low-power RF receiver frontend with tunable matching networks
    Patent number: 9929760
    Abstract: A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Lin Chu, Hsieh-Hung Hsieh, Tzu-Jin Yeh
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20180006146
    Abstract: A semiconductor device includes a plurality of fins over a substrate. Each fin of the plurality of fins extends in a first direction substantially perpendicular to a bottom surface of the substrate, and each fin of the plurality of fins comprises a first doped region having a first dopant type. The semiconductor device further includes an isolation region over the substrate between a first fin of the plurality of fins and a second fin of the plurality of fins adjacent to the first fin. The semiconductor device further includes a second doped region extends continuously across the isolation region, the second doped region extends into each fin of the plurality of fins, and a dimension of the second doped region in the isolation region in a second direction perpendicular to the first direction is less than a dimension of the at least one isolation region in the second direction.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Inventors: Chewn-Pu JOU, Tzu-Jin YEH, Chia-Chung CHEN
  • BURIED CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20170352660
    Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
  • Transistor with Asymmetric Source and Drain Regions
    Publication number: 20170345930
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Application
    Filed: November 2, 2016
    Publication date: November 30, 2017
    Inventors: HSIEN-YUAN LIAO, CHIEN-CHIH HO, CHI-HSIEN LIN, HUA-CHOU TSENG, HO-HSIANG CHEN, RU-GUN LIU, TZU-JIN YEH, YING-TA LU
  • Low noise amplifier having transformer feedback and method of using the same
    Patent number: 9831832
    Abstract: A low noise amplifier (LNA) includes a first transistor and a second transistor. A source of the second transistor is connected to a drain of the first transistor. The LNA further includes a feedback transformer. A gate of the first transistor is connected to a primary winding of the feedback transformer and a gate of the second transistor is connected to a secondary winding of the feedback transformer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Tzu-Jin Yeh
  • Ultra-Low-Power RF Receiver Frontend With Tunable Matching Networks
    Publication number: 20170302316
    Abstract: A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.
    Type: Application
    Filed: April 14, 2016
    Publication date: October 19, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Lin CHU, Hsieh-Hung HSIEH, Tzu-Jin YEH
  • Power cell and power cell circuit for a power amplifier
    Patent number: 9780211
    Abstract: A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chewn-Pu Jou, Tzu-Jin Yeh, Chia-Chung Chen
  • Buried channel semiconductor device and method for manufacturing the same
    Patent number: 9761584
    Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu