Abstract: Embodiments for optimizing dynamic resource allocations in a disaggregated computing environment. Data access patterns of data elements associated with a set of workloads are tracked across predetermined windows of time. The set of workloads is categorized into at least one of a plurality of classes, each class characterized by a method of data access of the data elements during the tracking of the data access patterns. Resource allocations are optimized in the disaggregated computing environment for a current iteration of the set of workloads based on the method of data access by allocating specific resources within the disaggregated data center to the current iteration of the set of workloads according to the data access patterns in real-time.

Abstract: A determination is made that a unit of memory that provides storage for one or more in-memory configuration state registers is to be pinned in a system that includes a guest operating system and one or more hosts at one or more host levels. Based on determining that the unit of memory is to be pinned, at least one host of the one or more hosts is notified that the unit of memory is to be pinned.

Abstract: A music practice feedback system, includes a processor; and a memory storing instructions that cause the processor to perform, forecasting an ability to retain playing skills of a sheet music by a user via machine learning and changing a display of the sheet music based on the forecasted ability.

Abstract: Embodiments for performing rolling software upgrades in a disaggregated computing environment. A rolling upgrade manager is provided for upgrading one or more disaggregated servers. A designated memory area is used for storing an updated software component, and a disaggregated server is switched to the designated memory area from a currently assigned memory area when performing the software upgrade. A process state and program data is maintained in the currently assigned memory area while maintaining the updated software component in the designated memory area such that the process state and program data are read from the currently assigned memory area and the updated software component is read from the designated memory area during currently executing operations of the disaggregated server.

Abstract: Snapshots are shared across save requests. A request to take a snapshot of one or more architected registers is obtained, and a determination is made as to whether the one or more architected registers have been modified since a previous snapshot that includes the one or more architected registers was taken. Based on determining the one or more architected registers have not been modified, the previous snapshot is used to satisfy the request to take the snapshot.

Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.

Abstract: In one embodiment, in accordance with the present invention, a method, computer program product, and system for performing actions based on captured interpersonal interactions during a meeting is provided. One or more computer processors capture the interpersonal interactions between people in a physical space during a period of time, using machine learning algorithms to detect the interpersonal interactions and a state of each person based on vision and audio sensors in the physical space. The one or more computer processors analyze and categorize the interactions and state of each person, and tag representations of each person with the respectively analyzed and categorized interactions and states of the respective person over the period of time. The one or more computer processors then take an action based on the analysis.

Abstract: Embodiments include techniques to generate alerts based at least in part on predicted mood responses to received electronic communications that include receiving, using a processor system, a communication, and analyzing, using the processor system, contents of the communication. The techniques also include based at least in part on results of the analysis, predicting, using a machine learning system, a cognitive response of a recipient of the communication, and based at least in part on the predicted cognitive response, executing an alerting operation.

Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.

Abstract: Branch prediction is suppressed for branch instructions executing in a transaction of a transactional memory (TM) environment in transactions that are re-executions of previously aborted transactions.

Abstract: Embodiments for optimizing memory placement in a disaggregated computing environment. A new workload is assigned to a subset of a plurality of processors, the subset of processors assigned a subset of a plurality of memory devices. In some embodiments, a determination is made as to whether the new workload is categorized as a memory-dependent workload having a memory need which can be met primarily by the subset of the memory devices. If the new workload is categorized as a memory-dependent workload, a determination is then made as to whether the subset of the memory devices is meeting the memory need of the new workload. When the subset of the memory devices is not meeting the memory need of the new workload, a memory related action is taken.

Abstract: Predicting a predicted value to be used in register-indirect branching. The predicted value is stored in a first selected location and a second selected location accessible to one or more instructions of a computing environment. The storing is performed concurrently to processing a register-indirect branch. Further, the first selected location and the second selected location is in addition to another location used to store an instruction address. The predicted value is used in speculative processing that includes the register-indirect branch.

Abstract: Providing control over processing of a prefetch request in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. A processor generates a prefetch request and a tag that dictates processing the prefect request. A processor sends the prefetch request and the tag to a second processor. A processor generates a conflict indication based on whether a concurrent processing of the prefetch request and an atomic transaction by the second processor would generate a conflict with a memory access that is associated with the atomic transaction. Based on an analysis of the conflict indication and the tag, a processor processes (i) either the prefetch request or the atomic transaction, or (ii) both the prefetch request and the atomic transaction.

Abstract: Direct inter-processor communication is enabled with respect to data in a memory location without having to switch specific circuits through a switching element (e.g., an optical switch). Rather, in this approach a memory pool is augmented to include a dedicated portion that serves as a disaggregated memory common space for communicating processors. The approach obviates the requirement of switching of physical memory modules through the optical switch to enable the processor-to-processor communication. Rather, processors (communicating with another) have an overlapping ability to access the same memory module in the pool; thus, there is no longer a need to change physical optical switch circuits to facilitate the inter-processor communication. The disaggregated memory common space is shared among the processors, which can access the common space for reads and writes, although particular locations in the memory common space for reads and writes are different.

Abstract: MapReduce processing is carried out in a disaggregated compute environment comprising a set of resource pools that comprise a processor pool, and a memory pool. Upon receipt of a MapReduce job, a task scheduler allocates resources from the set of resource pools, the resources including one or more processors drawn from the processor pool, and one or more memory modules drawn from the memory pool. The task scheduler then schedules a set of tasks required by the MapReduce job. At least one particular task in the set is scheduled irrespective of a location of data required for the particular task. In association with a shuffle phase of the MapReduce job, and in connection with the particular task, at least one connection between a processor and at least one memory module is dynamically rewired based on the location of the data required for the particular task, thereby obviating network transfer of that data.

Abstract: Embodiments are provided herein for component composition of a disaggregated computing system. A plurality of general purpose links connecting a computing element to other hardware elements are provided within the disaggregated computing system. Each of the plurality of general purpose links comprise a point-to-point connection to at least one of the other hardware elements such that the plurality of general purpose links conform to a configuration used by the other hardware elements regardless of a type of data being transferred through the plurality of general purpose links.

Abstract: Processing prefetch memory operations and transactions. A local processor receives a write prefetch request from a remote processor. Prior to execution of a write prefetch request received from a remote processor, determining whether a priority of the write prefetch request is greater than a priority of a pending transaction of a local processor. The write prefetch request is executed in response to a determination that the priority of the write prefetch request is greater than the priority of a pending transaction. Prefetch data produced by execution of the write prefetch request is provided to the remote processor.

Abstract: Predicting a predicted value to be used in register-indirect branching. The predicted value is stored in a first selected location and a second selected location accessible to one or more instructions of a computing environment. The storing is performed concurrently to processing a register-indirect branch. Further, the first selected location and the second selected location is in addition to another location used to store an instruction address. The predicted value is used in speculative processing that includes the register-indirect branch.

Abstract: A fusion opportunity is detected for a sequence of instructions. The sequence of instructions include an indication of an affiliated location and an indication of an affiliated derived location. Based on the detecting, a value to be stored in the affiliated derived location is generated. The value is a predicted value. The value is stored in the affiliated derived location, and the affiliated derived location is accessed to use the value by one or more instructions executing within the computing environment.

Abstract: Bulk store and load operations of configuration state registers. An instruction to perform a bulk operation for a group of configuration state registers having a common characteristic is executed. To perform the bulk operation for the group of configuration state registers, a plurality of operations is performed, and based on performing the plurality of operations, the instruction is completed.